Gitiles
Code Review Sign In
gerrit.cesnet.cz / github / trini / u-boot / d2ebaa41ede51f1ebf7e6e41a611c2efa89431e9 / . / board / ti / panda / panda_mux_data.h
blob: 5939257ff12fefd5c9653cc4594dca56ba220bb1 [file] [log] [blame]
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]1/*
2 * (C) Copyright 2010
3 * Texas Instruments Incorporated, <www.ti.com>
4 *
5 * Balaji Krishnamoorthy <balajitk@ti.com>
6 * Aneesh V <aneesh@ti.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
Aneesh V43de24f2011-09-08 11:06:06 -0400[diff] [blame]26#ifndef _PANDA_MUX_DATA_H_
27#define _PANDA_MUX_DATA_H_
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]28
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]29#include <asm/arch/mux_omap4.h>
30
Sricharan508a58f2011-11-15 09:49:55 -0500[diff] [blame]31
32const struct pad_conf_entry core_padconf_array_essential[] = {
33
34{GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
35{GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
36{GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
37{GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
38{GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
39{GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
40{GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
41{GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
42{GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
43{GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
44{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
45{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
46{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
47{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
48{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
49{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
50{SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */
51{SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */
52{SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */
53{SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */
54{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
55{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
56{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
57{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
58{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
59{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
60{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
61{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */
62{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
63{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
64{UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */
SRICHARAN Rd2ebaa42012-07-18 14:54:47 -0700[diff] [blame^]65{UART3_TX_IRTX, (M0)}, /* uart3_tx */
66{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
67{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */
68{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */
69{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */
70{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */
71{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */
72{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */
73{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */
74{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
75{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
76{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
77{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
78{USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */
79{USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */
80{USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */
81{USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */
82{UNIPRO_TY2, (PTU | IEN | M3)}, /* gpio_1 */
83{GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_62 */
84{FREF_CLK2_OUT, (PTU | IEN | M3)}, /* gpio_182 */
Sricharan508a58f2011-11-15 09:49:55 -0500[diff] [blame]85
86};
87
88const struct pad_conf_entry wkup_padconf_array_essential[] = {
89
90{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
91{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
SRICHARAN Rd2ebaa42012-07-18 14:54:47 -0700[diff] [blame^]92{PAD1_SYS_32K, (IEN | M0)}, /* sys_32k */
93{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
Sricharan508a58f2011-11-15 09:49:55 -0500[diff] [blame]94
95};
96
97const struct pad_conf_entry wkup_padconf_array_essential_4460[] = {
98
Nishanth Menon3acb5532012-03-01 14:17:38 +0000[diff] [blame]99{PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 for TPS: Mode 3 */
Sricharan508a58f2011-11-15 09:49:55 -0500[diff] [blame]100
101};
102
Aneesh V469ec1e2011-07-21 09:10:01 -0400[diff] [blame]103const struct pad_conf_entry core_padconf_array_non_essential[] = {
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]104 {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */
105 {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */
106 {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */
107 {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */
108 {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */
109 {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */
110 {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */
111 {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */
112 {GPMC_A16, (M3)}, /* gpio_40 */
113 {GPMC_A17, (PTD | M3)}, /* gpio_41 */
114 {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */
115 {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */
116 {GPMC_A20, (IEN | M3)}, /* gpio_44 */
117 {GPMC_A21, (M3)}, /* gpio_45 */
Aneesh V43de24f2011-09-08 11:06:06 -0400[diff] [blame]118 {GPMC_A22, (M3)}, /* gpio_46 */
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]119 {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */
120 {GPMC_A24, (PTD | M3)}, /* gpio_48 */
121 {GPMC_A25, (PTD | M3)}, /* gpio_49 */
122 {GPMC_NCS0, (M3)}, /* gpio_50 */
123 {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */
124 {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */
125 {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */
126 {GPMC_NWP, (M3)}, /* gpio_54 */
127 {GPMC_CLK, (PTD | M3)}, /* gpio_55 */
128 {GPMC_NADV_ALE, (M3)}, /* gpio_56 */
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]129 {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */
130 {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */
131 {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]132 {C2C_DATA11, (PTD | M3)}, /* gpio_100 */
Aneesh V43de24f2011-09-08 11:06:06 -0400[diff] [blame]133 {C2C_DATA12, (PTU | IEN | M3)}, /* gpio_101 */
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]134 {C2C_DATA13, (PTD | M3)}, /* gpio_102 */
135 {C2C_DATA14, (M1)}, /* dsi2_te0 */
136 {C2C_DATA15, (PTD | M3)}, /* gpio_104 */
137 {HDMI_HPD, (M0)}, /* hdmi_hpd */
138 {HDMI_CEC, (M0)}, /* hdmi_cec */
139 {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */
140 {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */
141 {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */
142 {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */
143 {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */
144 {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */
145 {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */
146 {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */
147 {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */
148 {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */
149 {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */
150 {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */
151 {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */
152 {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */
153 {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */
154 {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */
155 {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */
156 {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */
157 {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]158 {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */
159 {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */
160 {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */
Aneesh V43de24f2011-09-08 11:06:06 -0400[diff] [blame]161 {ABE_MCBSP1_CLKX, (IEN | M0)}, /* abe_mcbsp1_clkx */
162 {ABE_MCBSP1_DR, (IEN | M0)}, /* abe_mcbsp1_dr */
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]163 {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */
164 {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */
165 {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */
166 {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */
167 {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */
168 {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */
169 {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */
170 {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */
171 {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */
Aneesh V43de24f2011-09-08 11:06:06 -0400[diff] [blame]172 {ABE_DMIC_DIN2, (PTU | IEN | M3)}, /* gpio_121 */
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]173 {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */
Tero Kristo954211c2012-04-25 06:05:19 +0000[diff] [blame]174 {UART2_CTS, (PTU | IEN | M7)}, /* uart2_cts */
175 {UART2_RTS, (M7)}, /* uart2_rts */
176 {UART2_RX, (PTU | IEN | M7)}, /* uart2_rx */
177 {UART2_TX, (M7)}, /* uart2_tx */
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]178 {HDQ_SIO, (M3)}, /* gpio_127 */
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]179 {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */
180 {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */
181 {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */
182 {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */
183 {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */
184 {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */
185 {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]186 {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */
187 {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */
188 {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */
189 {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */
190 {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */
191 {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */
192 {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */
193 {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */
194 {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */
195 {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */
196 {UART4_RX, (IEN | M0)}, /* uart4_rx */
197 {UART4_TX, (M0)}, /* uart4_tx */
Aneesh V43de24f2011-09-08 11:06:06 -0400[diff] [blame]198 {USBB2_ULPITLL_CLK, (IEN | M3)}, /* gpio_157 */
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]199 {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */
200 {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */
201 {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */
202 {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */
203 {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */
204 {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */
205 {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */
206 {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */
207 {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */
208 {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */
209 {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */
210 {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */
211 {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */
Aneesh V43de24f2011-09-08 11:06:06 -0400[diff] [blame]212 {UNIPRO_TX0, (PTD | IEN | M3)}, /* gpio_171 */
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]213 {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */
214 {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */
215 {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */
Aneesh V43de24f2011-09-08 11:06:06 -0400[diff] [blame]216 {UNIPRO_TX2, (PTU | IEN | M3)}, /* gpio_0 */
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]217 {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */
218 {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */
219 {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */
220 {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */
221 {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */
222 {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */
223 {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */
224 {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */
225 {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */
226 {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]227 {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */
Aneesh V43de24f2011-09-08 11:06:06 -0400[diff] [blame]228 {SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]229 {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */
230 {SYS_BOOT1, (M3)}, /* gpio_185 */
231 {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */
Aneesh V43de24f2011-09-08 11:06:06 -0400[diff] [blame]232 {SYS_BOOT3, (M3)}, /* gpio_187 */
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]233 {SYS_BOOT4, (M3)}, /* gpio_188 */
234 {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */
235 {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */
236 {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */
237 {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */
238 {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */
239 {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */
240 {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */
241 {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */
242 {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */
243 {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */
244 {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */
245 {DPM_EMU10, (IEN | M5)}, /* dispc2_de */
246 {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */
247 {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */
248 {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */
249 {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */
250 {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */
251 {DPM_EMU16, (M3)}, /* gpio_27 */
252 {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */
253 {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */
254 {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */
255};
256
Ricardo Salveti de Araujo53430a42011-09-21 10:17:31 +0000[diff] [blame]257const struct pad_conf_entry core_padconf_array_non_essential_4430[] = {
258 {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */
259};
260
261const struct pad_conf_entry core_padconf_array_non_essential_4460[] = {
262 {ABE_MCBSP2_CLKX, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* led status_1 */
263};
264
Aneesh V469ec1e2011-07-21 09:10:01 -0400[diff] [blame]265const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]266 {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */
267 {PAD1_SIM_CLK, (M0)}, /* sim_clk */
268 {PAD0_SIM_RESET, (M0)}, /* sim_reset */
269 {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */
270 {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]271 {PAD1_FREF_XTAL_IN, (M0)}, /* # */
272 {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */
273 {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */
274 {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */
Sricharan508a58f2011-11-15 09:49:55 -0500[diff] [blame]275 {PAD1_FREF_CLK3_REQ, M7}, /* safe mode */
Aneesh V43de24f2011-09-08 11:06:06 -0400[diff] [blame]276 {PAD0_FREF_CLK4_OUT, (PTU | M3)}, /* led status_2 */
Steve Sakoman2ad853c2010-07-15 13:43:10 -0700[diff] [blame]277 {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */
278 {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */
279 {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */
280 {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */
281 {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */
282 {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */
283};
284
Ricardo Salveti de Araujo53430a42011-09-21 10:17:31 +0000[diff] [blame]285const struct pad_conf_entry wkup_padconf_array_non_essential_4430[] = {
286 {PAD1_FREF_CLK4_REQ, (PTU | M3)}, /* led status_1 */
287};
288
Aneesh V43de24f2011-09-08 11:06:06 -0400[diff] [blame]289#endif /* _PANDA_MUX_DATA_H_ */