| Dinh Nguyen | 3da4285 | 2015-06-02 22:52:49 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright Altera Corporation (C) 2012-2015 |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | |
| 8 | #define RW_MGR_READ_B2B_WAIT2 0x6A |
| 9 | #define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31 |
| 10 | #define RW_MGR_REFRESH_ALL 0x14 |
| 11 | #define RW_MGR_ZQCL 0x06 |
| 12 | #define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22 |
| 13 | #define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23 |
| 14 | #define RW_MGR_ACTIVATE_0_AND_1 0x0D |
| 15 | #define RW_MGR_MRS2_MIRR 0x0A |
| 16 | #define RW_MGR_INIT_RESET_0_CKE_0 0x6E |
| 17 | #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45 |
| 18 | #define RW_MGR_ACTIVATE_1 0x0F |
| 19 | #define RW_MGR_MRS2 0x04 |
| 20 | #define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34 |
| 21 | #define RW_MGR_MRS1 0x03 |
| 22 | #ifdef CONFIG_SOCFPGA_ARRIA5 |
| 23 | /* The if..else... is not required if generated by tools */ |
| 24 | #define RW_MGR_IDLE_LOOP1 0x7A |
| 25 | #else |
| 26 | #define RW_MGR_IDLE_LOOP1 0x7C |
| 27 | #endif /* CONFIG_SOCFPGA_ARRIA5 */ |
| 28 | #define RW_MGR_GUARANTEED_WRITE_WAIT2 0x18 |
| 29 | #define RW_MGR_MRS3 0x05 |
| 30 | #ifdef CONFIG_SOCFPGA_ARRIA5 |
| 31 | /* The if..else... is not required if generated by tools */ |
| 32 | #define RW_MGR_IDLE_LOOP2 0x79 |
| 33 | #else |
| 34 | #define RW_MGR_IDLE_LOOP2 0x7B |
| 35 | #endif /* CONFIG_SOCFPGA_ARRIA5 */ |
| 36 | #define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E |
| 37 | #define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24 |
| 38 | #define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C |
| 39 | #ifdef CONFIG_SOCFPGA_ARRIA5 |
| 40 | /* The if..else... is not required if generated by tools */ |
| 41 | #define RW_MGR_RDIMM_CMD 0x78 |
| 42 | #else |
| 43 | #define RW_MGR_RDIMM_CMD 0x7A |
| 44 | #endif /* CONFIG_SOCFPGA_ARRIA5 */ |
| 45 | #define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36 |
| 46 | #define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A |
| 47 | #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38 |
| 48 | #define RW_MGR_GUARANTEED_READ_CONT 0x53 |
| 49 | #define RW_MGR_MRS3_MIRR 0x0B |
| 50 | #define RW_MGR_IDLE 0x00 |
| 51 | #define RW_MGR_READ_B2B 0x58 |
| 52 | #define RW_MGR_INIT_RESET_0_CKE_0_inloop 0x6F |
| 53 | #define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37 |
| 54 | #define RW_MGR_GUARANTEED_WRITE 0x17 |
| 55 | #define RW_MGR_PRECHARGE_ALL 0x12 |
| 56 | #define RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74 |
| 57 | #ifdef CONFIG_SOCFPGA_ARRIA5 |
| 58 | /* The if..else... is not required if generated by tools */ |
| 59 | #define RW_MGR_SGLE_READ 0x7C |
| 60 | #else |
| 61 | #define RW_MGR_SGLE_READ 0x7E |
| 62 | #endif /* CONFIG_SOCFPGA_ARRIA5 */ |
| 63 | #define RW_MGR_MRS0_USER_MIRR 0x0C |
| 64 | #define RW_MGR_RETURN 0x01 |
| 65 | #define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35 |
| 66 | #define RW_MGR_MRS0_USER 0x07 |
| 67 | #define RW_MGR_GUARANTEED_READ 0x4B |
| 68 | #define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 |
| 69 | #define RW_MGR_INIT_RESET_1_CKE_0 0x73 |
| 70 | #define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 |
| 71 | #define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20 |
| 72 | #define RW_MGR_MRS0_DLL_RESET 0x02 |
| 73 | #define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E |
| 74 | #define RW_MGR_LFSR_WR_RD_BANK_0 0x21 |
| 75 | #define RW_MGR_CLEAR_DQS_ENABLE 0x48 |
| 76 | #define RW_MGR_MRS1_MIRR 0x09 |
| 77 | #define RW_MGR_READ_B2B_WAIT1 0x60 |
| 78 | #define RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680 |
| 79 | #define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680 |
| 80 | #define RW_MGR_CONTENT_REFRESH_ALL 0x000980 |
| 81 | #define RW_MGR_CONTENT_ZQCL 0x008380 |
| 82 | #define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700 |
| 83 | #define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00 |
| 84 | #define RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800 |
| 85 | #define RW_MGR_CONTENT_MRS2_MIRR 0x008580 |
| 86 | #define RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000 |
| 87 | #define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680 |
| 88 | #define RW_MGR_CONTENT_ACTIVATE_1 0x000880 |
| 89 | #define RW_MGR_CONTENT_MRS2 0x008280 |
| 90 | #define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00 |
| 91 | #define RW_MGR_CONTENT_MRS1 0x008200 |
| 92 | #define RW_MGR_CONTENT_IDLE_LOOP1 0x00A680 |
| 93 | #define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8 |
| 94 | #define RW_MGR_CONTENT_MRS3 0x008300 |
| 95 | #define RW_MGR_CONTENT_IDLE_LOOP2 0x008680 |
| 96 | #define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88 |
| 97 | #define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0 |
| 98 | #define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88 |
| 99 | #define RW_MGR_CONTENT_RDIMM_CMD 0x009180 |
| 100 | #define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700 |
| 101 | #define RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8 |
| 102 | #define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0 |
| 103 | #define RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168 |
| 104 | #define RW_MGR_CONTENT_MRS3_MIRR 0x008600 |
| 105 | #define RW_MGR_CONTENT_IDLE 0x080000 |
| 106 | #define RW_MGR_CONTENT_READ_B2B 0x040E88 |
| 107 | #define RW_MGR_CONTENT_INIT_RESET_0_CKE_0_inloop 0x000000 |
| 108 | #define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00 |
| 109 | #define RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68 |
| 110 | #define RW_MGR_CONTENT_PRECHARGE_ALL 0x000900 |
| 111 | #define RW_MGR_CONTENT_INIT_RESET_1_CKE_0_inloop_1 0x000080 |
| 112 | #define RW_MGR_CONTENT_SGLE_READ 0x040F08 |
| 113 | #define RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400 |
| 114 | #define RW_MGR_CONTENT_RETURN 0x080680 |
| 115 | #define RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80 |
| 116 | #define RW_MGR_CONTENT_MRS0_USER 0x008100 |
| 117 | #define RW_MGR_CONTENT_GUARANTEED_READ 0x001168 |
| 118 | #define RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480 |
| 119 | #define RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080 |
| 120 | #define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680 |
| 121 | #define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00 |
| 122 | #define RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180 |
| 123 | #define RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680 |
| 124 | #define RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80 |
| 125 | #define RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158 |
| 126 | #define RW_MGR_CONTENT_MRS1_MIRR 0x008500 |
| 127 | #define RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680 |
| 128 | |