blob: 15dab1d904239accc3676956ec5a8acbf3d8e444 [file] [log] [blame]
Adrian Alonso50a082a2015-09-02 13:54:15 -05001/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <asm/io.h>
8#include <asm/arch/imx-regs.h>
9#include <asm/arch/clock.h>
10#include <asm/arch/sys_proto.h>
11#include <asm/imx-common/boot_mode.h>
12#include <asm/arch/crm_regs.h>
13
14void init_aips(void)
15{
Adrian Alonso75a565f2015-09-02 13:54:20 -050016 struct aipstz_regs *aips1, *aips2, *aips3;
Adrian Alonso50a082a2015-09-02 13:54:15 -050017
18 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
19 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
Adrian Alonso50a082a2015-09-02 13:54:15 -050020 aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
Adrian Alonso50a082a2015-09-02 13:54:15 -050021
22 /*
23 * Set all MPROTx to be non-bufferable, trusted for R/W,
24 * not forced to user-mode.
25 */
26 writel(0x77777777, &aips1->mprot0);
27 writel(0x77777777, &aips1->mprot1);
28 writel(0x77777777, &aips2->mprot0);
29 writel(0x77777777, &aips2->mprot1);
30
31 /*
32 * Set all OPACRx to be non-bufferable, not require
33 * supervisor privilege level for access,allow for
34 * write access and untrusted master access.
35 */
36 writel(0x00000000, &aips1->opacr0);
37 writel(0x00000000, &aips1->opacr1);
38 writel(0x00000000, &aips1->opacr2);
39 writel(0x00000000, &aips1->opacr3);
40 writel(0x00000000, &aips1->opacr4);
41 writel(0x00000000, &aips2->opacr0);
42 writel(0x00000000, &aips2->opacr1);
43 writel(0x00000000, &aips2->opacr2);
44 writel(0x00000000, &aips2->opacr3);
45 writel(0x00000000, &aips2->opacr4);
46
Peng Fanf697c2a2015-09-15 14:05:08 +080047 if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) {
Adrian Alonso75a565f2015-09-02 13:54:20 -050048 /*
49 * Set all MPROTx to be non-bufferable, trusted for R/W,
50 * not forced to user-mode.
51 */
52 writel(0x77777777, &aips3->mprot0);
53 writel(0x77777777, &aips3->mprot1);
Adrian Alonso50a082a2015-09-02 13:54:15 -050054
Adrian Alonso75a565f2015-09-02 13:54:20 -050055 /*
56 * Set all OPACRx to be non-bufferable, not require
57 * supervisor privilege level for access,allow for
58 * write access and untrusted master access.
59 */
60 writel(0x00000000, &aips3->opacr0);
61 writel(0x00000000, &aips3->opacr1);
62 writel(0x00000000, &aips3->opacr2);
63 writel(0x00000000, &aips3->opacr3);
64 writel(0x00000000, &aips3->opacr4);
65 }
Adrian Alonso50a082a2015-09-02 13:54:15 -050066}
67
Adrian Alonso648539c2015-09-02 13:54:21 -050068void imx_set_wdog_powerdown(bool enable)
69{
70 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
71 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
72 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
73#ifdef CONFIG_MX7D
74 struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
75#endif
76
77 /* Write to the PDE (Power Down Enable) bit */
78 writew(enable, &wdog1->wmcr);
79 writew(enable, &wdog2->wmcr);
80
81 if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
82 is_soc_type(MXC_SOC_MX7))
83 writew(enable, &wdog3->wmcr);
84#ifdef CONFIG_MX7D
85 writew(enable, &wdog4->wmcr);
86#endif
87}
88
Adrian Alonso50a082a2015-09-02 13:54:15 -050089#define SRC_SCR_WARM_RESET_ENABLE 0
90
91void init_src(void)
92{
93 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
94 u32 val;
95
96 /*
97 * force warm reset sources to generate cold reset
98 * for a more reliable restart
99 */
100 val = readl(&src_regs->scr);
101 val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
102 writel(val, &src_regs->scr);
103}
104
Peng Fan4406da02015-09-15 14:05:06 +0800105#ifdef CONFIG_CMD_BMODE
Adrian Alonso50a082a2015-09-02 13:54:15 -0500106void boot_mode_apply(unsigned cfg_val)
107{
108 unsigned reg;
109 struct src *psrc = (struct src *)SRC_BASE_ADDR;
110 writel(cfg_val, &psrc->gpr9);
111 reg = readl(&psrc->gpr10);
112 if (cfg_val)
113 reg |= 1 << 28;
114 else
115 reg &= ~(1 << 28);
116 writel(reg, &psrc->gpr10);
117}
Peng Fan4406da02015-09-15 14:05:06 +0800118#endif