| Dirk Behme | 2c80321 | 2008-12-14 09:47:11 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2006-2008 |
| 3 | * Texas Instruments, <www.ti.com> |
| 4 | * Richard Woodruff <r-woodruff2@ti.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 19 | * MA 02111-1307 USA |
| 20 | */ |
| 21 | #ifndef _CLOCKS_OMAP3_H_ |
| 22 | #define _CLOCKS_OMAP3_H_ |
| 23 | |
| 24 | #define PLL_STOP 1 /* PER & IVA */ |
| 25 | #define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ |
| 26 | #define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ |
| 27 | #define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ |
| 28 | |
| 29 | /* |
| 30 | * The following configurations are OPP and SysClk value independant |
| 31 | * and hence are defined here. All the other DPLL related values are |
| 32 | * tabulated in lowlevel_init.S. |
| 33 | */ |
| 34 | |
| 35 | /* CORE DPLL */ |
| 36 | #define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ |
| 37 | #define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ |
| 38 | #define CORE_FUSB_DIV 2 /* 41.5MHz: */ |
| 39 | #define CORE_L4_DIV 2 /* 83MHz : L4 */ |
| 40 | #define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ |
| 41 | #define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ |
| 42 | #define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ |
| 43 | |
| 44 | /* PER DPLL */ |
| 45 | #define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ |
| 46 | #define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ |
| 47 | #define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */ |
| 48 | #define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ |
| 49 | |
| 50 | #define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50)) |
| 51 | |
| 52 | /* MPU DPLL */ |
| 53 | |
| 54 | #define MPU_M_12_ES1 0x0FE |
| 55 | #define MPU_N_12_ES1 0x07 |
| 56 | #define MPU_FSEL_12_ES1 0x05 |
| 57 | #define MPU_M2_12_ES1 0x01 |
| 58 | |
| 59 | #define MPU_M_12_ES2 0x0FA |
| 60 | #define MPU_N_12_ES2 0x05 |
| 61 | #define MPU_FSEL_12_ES2 0x07 |
| 62 | #define MPU_M2_ES2 0x01 |
| 63 | |
| 64 | #define MPU_M_12 0x085 |
| 65 | #define MPU_N_12 0x05 |
| 66 | #define MPU_FSEL_12 0x07 |
| 67 | #define MPU_M2_12 0x01 |
| 68 | |
| 69 | #define MPU_M_13_ES1 0x17D |
| 70 | #define MPU_N_13_ES1 0x0C |
| 71 | #define MPU_FSEL_13_ES1 0x03 |
| 72 | #define MPU_M2_13_ES1 0x01 |
| 73 | |
| 74 | #define MPU_M_13_ES2 0x1F4 |
| 75 | #define MPU_N_13_ES2 0x0C |
| 76 | #define MPU_FSEL_13_ES2 0x03 |
| 77 | #define MPU_M2_13_ES2 0x01 |
| 78 | |
| 79 | #define MPU_M_13 0x10A |
| 80 | #define MPU_N_13 0x0C |
| 81 | #define MPU_FSEL_13 0x03 |
| 82 | #define MPU_M2_13 0x01 |
| 83 | |
| 84 | #define MPU_M_19P2_ES1 0x179 |
| 85 | #define MPU_N_19P2_ES1 0x12 |
| 86 | #define MPU_FSEL_19P2_ES1 0x04 |
| 87 | #define MPU_M2_19P2_ES1 0x01 |
| 88 | |
| 89 | #define MPU_M_19P2_ES2 0x271 |
| 90 | #define MPU_N_19P2_ES2 0x17 |
| 91 | #define MPU_FSEL_19P2_ES2 0x03 |
| 92 | #define MPU_M2_19P2_ES2 0x01 |
| 93 | |
| 94 | #define MPU_M_19P2 0x14C |
| 95 | #define MPU_N_19P2 0x17 |
| 96 | #define MPU_FSEL_19P2 0x03 |
| 97 | #define MPU_M2_19P2 0x01 |
| 98 | |
| 99 | #define MPU_M_26_ES1 0x17D |
| 100 | #define MPU_N_26_ES1 0x19 |
| 101 | #define MPU_FSEL_26_ES1 0x03 |
| 102 | #define MPU_M2_26_ES1 0x01 |
| 103 | |
| 104 | #define MPU_M_26_ES2 0x0FA |
| 105 | #define MPU_N_26_ES2 0x0C |
| 106 | #define MPU_FSEL_26_ES2 0x07 |
| 107 | #define MPU_M2_26_ES2 0x01 |
| 108 | |
| 109 | #define MPU_M_26 0x085 |
| 110 | #define MPU_N_26 0x0C |
| 111 | #define MPU_FSEL_26 0x07 |
| 112 | #define MPU_M2_26 0x01 |
| 113 | |
| 114 | #define MPU_M_38P4_ES1 0x1FA |
| 115 | #define MPU_N_38P4_ES1 0x32 |
| 116 | #define MPU_FSEL_38P4_ES1 0x03 |
| 117 | #define MPU_M2_38P4_ES1 0x01 |
| 118 | |
| 119 | #define MPU_M_38P4_ES2 0x271 |
| 120 | #define MPU_N_38P4_ES2 0x2F |
| 121 | #define MPU_FSEL_38P4_ES2 0x03 |
| 122 | #define MPU_M2_38P4_ES2 0x01 |
| 123 | |
| 124 | #define MPU_M_38P4 0x14C |
| 125 | #define MPU_N_38P4 0x2F |
| 126 | #define MPU_FSEL_38P4 0x03 |
| 127 | #define MPU_M2_38P4 0x01 |
| 128 | |
| 129 | /* IVA DPLL */ |
| 130 | |
| 131 | #define IVA_M_12_ES1 0x07D |
| 132 | #define IVA_N_12_ES1 0x05 |
| 133 | #define IVA_FSEL_12_ES1 0x07 |
| 134 | #define IVA_M2_12_ES1 0x01 |
| 135 | |
| 136 | #define IVA_M_12_ES2 0x0B4 |
| 137 | #define IVA_N_12_ES2 0x05 |
| 138 | #define IVA_FSEL_12_ES2 0x07 |
| 139 | #define IVA_M2_12_ES2 0x01 |
| 140 | |
| 141 | #define IVA_M_12 0x085 |
| 142 | #define IVA_N_12 0x05 |
| 143 | #define IVA_FSEL_12 0x07 |
| 144 | #define IVA_M2_12 0x01 |
| 145 | |
| 146 | #define IVA_M_13_ES1 0x0FA |
| 147 | #define IVA_N_13_ES1 0x0C |
| 148 | #define IVA_FSEL_13_ES1 0x03 |
| 149 | #define IVA_M2_13_ES1 0x01 |
| 150 | |
| 151 | #define IVA_M_13_ES2 0x168 |
| 152 | #define IVA_N_13_ES2 0x0C |
| 153 | #define IVA_FSEL_13_ES2 0x03 |
| 154 | #define IVA_M2_13_ES2 0x01 |
| 155 | |
| 156 | #define IVA_M_13 0x10A |
| 157 | #define IVA_N_13 0x0C |
| 158 | #define IVA_FSEL_13 0x03 |
| 159 | #define IVA_M2_13 0x01 |
| 160 | |
| 161 | #define IVA_M_19P2_ES1 0x082 |
| 162 | #define IVA_N_19P2_ES1 0x09 |
| 163 | #define IVA_FSEL_19P2_ES1 0x07 |
| 164 | #define IVA_M2_19P2_ES1 0x01 |
| 165 | |
| 166 | #define IVA_M_19P2_ES2 0x0E1 |
| 167 | #define IVA_N_19P2_ES2 0x0B |
| 168 | #define IVA_FSEL_19P2_ES2 0x06 |
| 169 | #define IVA_M2_19P2_ES2 0x01 |
| 170 | |
| 171 | #define IVA_M_19P2 0x14C |
| 172 | #define IVA_N_19P2 0x17 |
| 173 | #define IVA_FSEL_19P2 0x03 |
| 174 | #define IVA_M2_19P2 0x01 |
| 175 | |
| 176 | #define IVA_M_26_ES1 0x07D |
| 177 | #define IVA_N_26_ES1 0x0C |
| 178 | #define IVA_FSEL_26_ES1 0x07 |
| 179 | #define IVA_M2_26_ES1 0x01 |
| 180 | |
| 181 | #define IVA_M_26_ES2 0x0B4 |
| 182 | #define IVA_N_26_ES2 0x0C |
| 183 | #define IVA_FSEL_26_ES2 0x07 |
| 184 | #define IVA_M2_26_ES2 0x01 |
| 185 | |
| 186 | #define IVA_M_26 0x085 |
| 187 | #define IVA_N_26 0x0C |
| 188 | #define IVA_FSEL_26 0x07 |
| 189 | #define IVA_M2_26 0x01 |
| 190 | |
| 191 | #define IVA_M_38P4_ES1 0x13F |
| 192 | #define IVA_N_38P4_ES1 0x30 |
| 193 | #define IVA_FSEL_38P4_ES1 0x03 |
| 194 | #define IVA_M2_38P4_ES1 0x01 |
| 195 | |
| 196 | #define IVA_M_38P4_ES2 0x0E1 |
| 197 | #define IVA_N_38P4_ES2 0x17 |
| 198 | #define IVA_FSEL_38P4_ES2 0x06 |
| 199 | #define IVA_M2_38P4_ES2 0x01 |
| 200 | |
| 201 | #define IVA_M_38P4 0x14C |
| 202 | #define IVA_N_38P4 0x2F |
| 203 | #define IVA_FSEL_38P4 0x03 |
| 204 | #define IVA_M2_38P4 0x01 |
| 205 | |
| 206 | /* CORE DPLL */ |
| 207 | |
| 208 | #define CORE_M_12 0xA6 |
| 209 | #define CORE_N_12 0x05 |
| 210 | #define CORE_FSEL_12 0x07 |
| 211 | #define CORE_M2_12 0x01 /* M3 of 2 */ |
| 212 | |
| 213 | #define CORE_M_12_ES1 0x19F |
| 214 | #define CORE_N_12_ES1 0x0E |
| 215 | #define CORE_FSL_12_ES1 0x03 |
| 216 | #define CORE_M2_12_ES1 0x1 /* M3 of 2 */ |
| 217 | |
| 218 | #define CORE_M_13 0x14C |
| 219 | #define CORE_N_13 0x0C |
| 220 | #define CORE_FSEL_13 0x03 |
| 221 | #define CORE_M2_13 0x01 /* M3 of 2 */ |
| 222 | |
| 223 | #define CORE_M_13_ES1 0x1B2 |
| 224 | #define CORE_N_13_ES1 0x10 |
| 225 | #define CORE_FSL_13_ES1 0x03 |
| 226 | #define CORE_M2_13_ES1 0x01 /* M3 of 2 */ |
| 227 | |
| 228 | #define CORE_M_19P2 0x19F |
| 229 | #define CORE_N_19P2 0x17 |
| 230 | #define CORE_FSEL_19P2 0x03 |
| 231 | #define CORE_M2_19P2 0x01 /* M3 of 2 */ |
| 232 | |
| 233 | #define CORE_M_19P2_ES1 0x19F |
| 234 | #define CORE_N_19P2_ES1 0x17 |
| 235 | #define CORE_FSL_19P2_ES1 0x03 |
| 236 | #define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */ |
| 237 | |
| 238 | #define CORE_M_26 0xA6 |
| 239 | #define CORE_N_26 0x0C |
| 240 | #define CORE_FSEL_26 0x07 |
| 241 | #define CORE_M2_26 0x01 /* M3 of 2 */ |
| 242 | |
| 243 | #define CORE_M_26_ES1 0x1B2 |
| 244 | #define CORE_N_26_ES1 0x21 |
| 245 | #define CORE_FSL_26_ES1 0x03 |
| 246 | #define CORE_M2_26_ES1 0x01 /* M3 of 2 */ |
| 247 | |
| 248 | #define CORE_M_38P4 0x19F |
| 249 | #define CORE_N_38P4 0x2F |
| 250 | #define CORE_FSEL_38P4 0x03 |
| 251 | #define CORE_M2_38P4 0x01 /* M3 of 2 */ |
| 252 | |
| 253 | #define CORE_M_38P4_ES1 0x19F |
| 254 | #define CORE_N_38P4_ES1 0x2F |
| 255 | #define CORE_FSL_38P4_ES1 0x03 |
| 256 | #define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */ |
| 257 | |
| 258 | /* PER DPLL */ |
| 259 | |
| 260 | #define PER_M_12 0xD8 |
| 261 | #define PER_N_12 0x05 |
| 262 | #define PER_FSEL_12 0x07 |
| 263 | #define PER_M2_12 0x09 |
| 264 | |
| 265 | #define PER_M_13 0x1B0 |
| 266 | #define PER_N_13 0x0C |
| 267 | #define PER_FSEL_13 0x03 |
| 268 | #define PER_M2_13 0x09 |
| 269 | |
| 270 | #define PER_M_19P2 0xE1 |
| 271 | #define PER_N_19P2 0x09 |
| 272 | #define PER_FSEL_19P2 0x07 |
| 273 | #define PER_M2_19P2 0x09 |
| 274 | |
| 275 | #define PER_M_26 0xD8 |
| 276 | #define PER_N_26 0x0C |
| 277 | #define PER_FSEL_26 0x07 |
| 278 | #define PER_M2_26 0x09 |
| 279 | |
| 280 | #define PER_M_38P4 0xE1 |
| 281 | #define PER_N_38P4 0x13 |
| 282 | #define PER_FSEL_38P4 0x07 |
| 283 | #define PER_M2_38P4 0x09 |
| 284 | |
| 285 | #endif /* endif _CLOCKS_OMAP3_H_ */ |