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Michal Simek18a952c2018-03-27 10:36:39 +02001// SPDX-License-Identifier: GPL-2.0+
Michal Simekee4983f2017-12-08 14:50:42 +01002/*
3 * Clock specification for Xilinx ZynqMP
4 *
Michal Simekd31f1c92020-02-18 08:38:06 +01005 * (C) Copyright 2017 - 2020, Xilinx, Inc.
Michal Simekee4983f2017-12-08 14:50:42 +01006 *
7 * Michal Simek <michal.simek@xilinx.com>
Michal Simekee4983f2017-12-08 14:50:42 +01008 */
9
Michal Simek039c7402019-10-14 15:42:03 +020010#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
Michal Simekee4983f2017-12-08 14:50:42 +010011/ {
12 fclk0: fclk0 {
Michal Simek039c7402019-10-14 15:42:03 +020013 status = "okay";
Michal Simekee4983f2017-12-08 14:50:42 +010014 compatible = "xlnx,fclk";
Michal Simek039c7402019-10-14 15:42:03 +020015 clocks = <&zynqmp_clk PL0_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +010016 };
17
18 fclk1: fclk1 {
Michal Simek039c7402019-10-14 15:42:03 +020019 status = "okay";
Michal Simekee4983f2017-12-08 14:50:42 +010020 compatible = "xlnx,fclk";
Michal Simek039c7402019-10-14 15:42:03 +020021 clocks = <&zynqmp_clk PL1_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +010022 };
23
24 fclk2: fclk2 {
Michal Simek039c7402019-10-14 15:42:03 +020025 status = "okay";
Michal Simekee4983f2017-12-08 14:50:42 +010026 compatible = "xlnx,fclk";
Michal Simek039c7402019-10-14 15:42:03 +020027 clocks = <&zynqmp_clk PL2_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +010028 };
29
30 fclk3: fclk3 {
Michal Simek039c7402019-10-14 15:42:03 +020031 status = "okay";
Michal Simekee4983f2017-12-08 14:50:42 +010032 compatible = "xlnx,fclk";
Michal Simek039c7402019-10-14 15:42:03 +020033 clocks = <&zynqmp_clk PL3_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +010034 };
35
36 pss_ref_clk: pss_ref_clk {
37 u-boot,dm-pre-reloc;
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <33333333>;
41 };
42
43 video_clk: video_clk {
44 u-boot,dm-pre-reloc;
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <27000000>;
48 };
49
50 pss_alt_ref_clk: pss_alt_ref_clk {
51 u-boot,dm-pre-reloc;
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <0>;
55 };
56
57 gt_crx_ref_clk: gt_crx_ref_clk {
58 u-boot,dm-pre-reloc;
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <108000000>;
62 };
63
64 aux_ref_clk: aux_ref_clk {
65 u-boot,dm-pre-reloc;
66 compatible = "fixed-clock";
67 #clock-cells = <0>;
68 clock-frequency = <27000000>;
69 };
70
Michal Simekee4983f2017-12-08 14:50:42 +010071 dp_aclk: dp_aclk {
72 compatible = "fixed-clock";
73 #clock-cells = <0>;
74 clock-frequency = <100000000>;
75 clock-accuracy = <100>;
76 };
77};
78
Michal Simek039c7402019-10-14 15:42:03 +020079&zynqmp_firmware {
80 zynqmp_clk: clock-controller {
81 u-boot,dm-pre-reloc;
82 #clock-cells = <1>;
83 compatible = "xlnx,zynqmp-clk";
84 clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
85 <&aux_ref_clk>, <&gt_crx_ref_clk>;
86 clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
87 "aux_ref_clk", "gt_crx_ref_clk";
88 };
89};
90
Michal Simekee4983f2017-12-08 14:50:42 +010091&can0 {
Michal Simek039c7402019-10-14 15:42:03 +020092 clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +010093};
94
95&can1 {
Michal Simek039c7402019-10-14 15:42:03 +020096 clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +010097};
98
99&cpu0 {
Michal Simek039c7402019-10-14 15:42:03 +0200100 clocks = <&zynqmp_clk ACPU>;
Michal Simekee4983f2017-12-08 14:50:42 +0100101};
102
103&fpd_dma_chan1 {
Michal Simek039c7402019-10-14 15:42:03 +0200104 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100105};
106
107&fpd_dma_chan2 {
Michal Simek039c7402019-10-14 15:42:03 +0200108 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100109};
110
111&fpd_dma_chan3 {
Michal Simek039c7402019-10-14 15:42:03 +0200112 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100113};
114
115&fpd_dma_chan4 {
Michal Simek039c7402019-10-14 15:42:03 +0200116 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100117};
118
119&fpd_dma_chan5 {
Michal Simek039c7402019-10-14 15:42:03 +0200120 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100121};
122
123&fpd_dma_chan6 {
Michal Simek039c7402019-10-14 15:42:03 +0200124 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100125};
126
127&fpd_dma_chan7 {
Michal Simek039c7402019-10-14 15:42:03 +0200128 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100129};
130
131&fpd_dma_chan8 {
Michal Simek039c7402019-10-14 15:42:03 +0200132 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100133};
134
135&gpu {
Michal Simek039c7402019-10-14 15:42:03 +0200136 clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100137};
138
139&lpd_dma_chan1 {
Michal Simek039c7402019-10-14 15:42:03 +0200140 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100141};
142
143&lpd_dma_chan2 {
Michal Simek039c7402019-10-14 15:42:03 +0200144 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100145};
146
147&lpd_dma_chan3 {
Michal Simek039c7402019-10-14 15:42:03 +0200148 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100149};
150
151&lpd_dma_chan4 {
Michal Simek039c7402019-10-14 15:42:03 +0200152 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100153};
154
155&lpd_dma_chan5 {
Michal Simek039c7402019-10-14 15:42:03 +0200156 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100157};
158
159&lpd_dma_chan6 {
Michal Simek039c7402019-10-14 15:42:03 +0200160 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100161};
162
163&lpd_dma_chan7 {
Michal Simek039c7402019-10-14 15:42:03 +0200164 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100165};
166
167&lpd_dma_chan8 {
Michal Simek039c7402019-10-14 15:42:03 +0200168 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100169};
170
171&nand0 {
Michal Simek039c7402019-10-14 15:42:03 +0200172 clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100173};
174
175&gem0 {
Michal Simekb0f36d52020-01-09 14:15:07 +0100176 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
177 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
178 <&zynqmp_clk GEM_TSU>;
Michal Simekee4983f2017-12-08 14:50:42 +0100179 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
180};
181
182&gem1 {
Michal Simekb0f36d52020-01-09 14:15:07 +0100183 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
184 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
185 <&zynqmp_clk GEM_TSU>;
Michal Simekee4983f2017-12-08 14:50:42 +0100186 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
187};
188
189&gem2 {
Michal Simekb0f36d52020-01-09 14:15:07 +0100190 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
191 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
192 <&zynqmp_clk GEM_TSU>;
Michal Simekee4983f2017-12-08 14:50:42 +0100193 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
194};
195
196&gem3 {
Michal Simekb0f36d52020-01-09 14:15:07 +0100197 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
198 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
199 <&zynqmp_clk GEM_TSU>;
Michal Simekee4983f2017-12-08 14:50:42 +0100200 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
201};
202
203&gpio {
Michal Simek039c7402019-10-14 15:42:03 +0200204 clocks = <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100205};
206
207&i2c0 {
Michal Simek039c7402019-10-14 15:42:03 +0200208 clocks = <&zynqmp_clk I2C0_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100209};
210
211&i2c1 {
Michal Simek039c7402019-10-14 15:42:03 +0200212 clocks = <&zynqmp_clk I2C1_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100213};
214
215&pcie {
Michal Simek039c7402019-10-14 15:42:03 +0200216 clocks = <&zynqmp_clk PCIE_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100217};
218
219&qspi {
Michal Simek039c7402019-10-14 15:42:03 +0200220 clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100221};
222
223&sata {
Michal Simek039c7402019-10-14 15:42:03 +0200224 clocks = <&zynqmp_clk SATA_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100225};
226
227&sdhci0 {
Michal Simek039c7402019-10-14 15:42:03 +0200228 clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100229};
230
231&sdhci1 {
Michal Simek039c7402019-10-14 15:42:03 +0200232 clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100233};
234
235&spi0 {
Michal Simek039c7402019-10-14 15:42:03 +0200236 clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100237};
238
239&spi1 {
Michal Simek039c7402019-10-14 15:42:03 +0200240 clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100241};
242
Rajan Vajaecb4d742018-04-25 05:34:04 -0700243&ttc0 {
Michal Simek039c7402019-10-14 15:42:03 +0200244 clocks = <&zynqmp_clk LPD_LSBUS>;
Rajan Vajaecb4d742018-04-25 05:34:04 -0700245};
246
247&ttc1 {
Michal Simek039c7402019-10-14 15:42:03 +0200248 clocks = <&zynqmp_clk LPD_LSBUS>;
Rajan Vajaecb4d742018-04-25 05:34:04 -0700249};
250
251&ttc2 {
Michal Simek039c7402019-10-14 15:42:03 +0200252 clocks = <&zynqmp_clk LPD_LSBUS>;
Rajan Vajaecb4d742018-04-25 05:34:04 -0700253};
254
255&ttc3 {
Michal Simek039c7402019-10-14 15:42:03 +0200256 clocks = <&zynqmp_clk LPD_LSBUS>;
Rajan Vajaecb4d742018-04-25 05:34:04 -0700257};
258
Michal Simekee4983f2017-12-08 14:50:42 +0100259&uart0 {
Michal Simek039c7402019-10-14 15:42:03 +0200260 clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100261};
262
263&uart1 {
Michal Simek039c7402019-10-14 15:42:03 +0200264 clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100265};
266
267&usb0 {
Michal Simek039c7402019-10-14 15:42:03 +0200268 clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100269};
270
271&usb1 {
Michal Simek039c7402019-10-14 15:42:03 +0200272 clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100273};
274
275&watchdog0 {
Michal Simek039c7402019-10-14 15:42:03 +0200276 clocks = <&zynqmp_clk WDT>;
Michal Simekee4983f2017-12-08 14:50:42 +0100277};
278
Michal Simek2038e462018-07-18 09:25:43 +0200279&lpd_watchdog {
280 clocks = <&zynqmp_clk LPD_WDT>;
281};
282
Michal Simekee4983f2017-12-08 14:50:42 +0100283&xilinx_ams {
Michal Simek039c7402019-10-14 15:42:03 +0200284 clocks = <&zynqmp_clk AMS_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100285};
286
Michal Simekce906542020-11-26 14:25:02 +0100287&zynqmp_pcap {
288 clocks = <&zynqmp_clk PCAP>;
Michal Simek04437de2020-02-18 09:24:08 +0100289};
290
Michal Simekce906542020-11-26 14:25:02 +0100291&zynqmp_dpdma {
Michal Simek039c7402019-10-14 15:42:03 +0200292 clocks = <&zynqmp_clk DPDMA_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100293};
294
Michal Simekce906542020-11-26 14:25:02 +0100295&zynqmp_dpsub {
296 clocks = <&zynqmp_clk TOPSW_LSBUS>,
297 <&zynqmp_clk DP_AUDIO_REF>,
298 <&zynqmp_clk DP_VIDEO_REF>;
Nava kishore Manne21620992019-10-18 18:07:32 +0200299};