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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +05302/*
3 * (C) Copyright 2015 Xilinx, Inc,
4 * Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +05305 */
6
7#ifndef _ZYNQMPPL_H_
8#define _ZYNQMPPL_H_
9
10#include <xilinx.h>
Simon Glasscd93d622020-05-10 11:40:13 -060011#include <linux/bitops.h>
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +053012
Michal Simek47e60cb2016-02-01 15:05:58 +010013#define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +053014#define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016
Nitin Jainb32e11a72018-02-16 17:29:54 +053015#define ZYNQMP_SIP_SVC_PM_FPGA_STATUS 0xC2000017
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +053016#define ZYNQMP_FPGA_OP_INIT (1 << 0)
17#define ZYNQMP_FPGA_OP_LOAD (1 << 1)
18#define ZYNQMP_FPGA_OP_DONE (1 << 2)
19
Siva Durga Prasad Paladugua18d09e2018-05-31 15:10:23 +053020#define ZYNQMP_FPGA_FLAG_AUTHENTICATED BIT(2)
21#define ZYNQMP_FPGA_FLAG_ENCRYPTED BIT(3)
22
Soren Brinkmann0cba6ab2016-09-29 11:44:41 -070023#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15
24#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xf << \
25 ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
26#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12
Michal Simek92687042017-06-28 15:40:32 +020027#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << ZYNQMP_CSU_IDCODE_SVD_SHIFT)
Soren Brinkmann0cba6ab2016-09-29 11:44:41 -070028
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +053029extern struct xilinx_fpga_op zynqmp_op;
30
31#define XILINX_ZYNQMP_DESC \
32{ xilinx_zynqmp, csu_dma, 1, &zynqmp_op, 0, &zynqmp_op }
33
34#endif /* _ZYNQMPPL_H_ */