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gerrit.cesnet.cz / github / trini / u-boot / cd3c67692b13fb24f69b3016bc9990eeaaa32ca1 / . / arch / arm / include / asm / arch-tegra124 / clock-tables.h
blob: 7005855999579819f4df14415521b6be62e4395d [file] [log] [blame]
Tom Warren999c6ba2014-01-24 12:46:13 -0700[diff] [blame]1/*
2 * (C) Copyright 2013
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8/* Tegra124 clock PLL tables */
9
10#ifndef _TEGRA124_CLOCK_TABLES_H_
11#define _TEGRA124_CLOCK_TABLES_H_
12
13/* The PLLs supported by the hardware */
14enum clock_id {
15 CLOCK_ID_FIRST,
16 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
17 CLOCK_ID_MEMORY,
18 CLOCK_ID_PERIPH,
19 CLOCK_ID_AUDIO,
20 CLOCK_ID_USB,
21 CLOCK_ID_DISPLAY,
22
23 /* now the simple ones */
24 CLOCK_ID_FIRST_SIMPLE,
25 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
26 CLOCK_ID_EPCI,
27 CLOCK_ID_SFROM32KHZ,
Simon Glass96e82a22015-04-14 21:03:34 -0600[diff] [blame]28 CLOCK_ID_DP, /* Special for Tegra124 */
Tom Warren999c6ba2014-01-24 12:46:13 -0700[diff] [blame]29
30 /* These are the base clocks (inputs to the Tegra SoC) */
31 CLOCK_ID_32KHZ,
32 CLOCK_ID_OSC,
33
34 CLOCK_ID_COUNT, /* number of PLLs */
35
36 /*
37 * These are clock IDs that are used in table clock_source[][]
38 * but will not be assigned as a clock source for any peripheral.
39 */
40 CLOCK_ID_DISPLAY2,
41 CLOCK_ID_CGENERAL2,
42 CLOCK_ID_CGENERAL3,
43 CLOCK_ID_MEMORY2,
44 CLOCK_ID_SRC2,
45
46 CLOCK_ID_NONE = -1,
47};
48
49/* The clocks supported by the hardware */
50enum periph_id {
51 PERIPH_ID_FIRST,
52
53 /* Low word: 31:0 (DEVICES_L) */
54 PERIPH_ID_CPU = PERIPH_ID_FIRST,
55 PERIPH_ID_COP,
56 PERIPH_ID_TRIGSYS,
57 PERIPH_ID_ISPB,
58 PERIPH_ID_RESERVED4,
59 PERIPH_ID_TMR,
60 PERIPH_ID_UART1,
61 PERIPH_ID_UART2,
62
63 /* 8 */
64 PERIPH_ID_GPIO,
65 PERIPH_ID_SDMMC2,
66 PERIPH_ID_SPDIF,
67 PERIPH_ID_I2S1,
68 PERIPH_ID_I2C1,
69 PERIPH_ID_RESERVED13,
70 PERIPH_ID_SDMMC1,
71 PERIPH_ID_SDMMC4,
72
73 /* 16 */
74 PERIPH_ID_TCW,
75 PERIPH_ID_PWM,
76 PERIPH_ID_I2S2,
77 PERIPH_ID_RESERVED19,
78 PERIPH_ID_VI,
79 PERIPH_ID_RESERVED21,
80 PERIPH_ID_USBD,
81 PERIPH_ID_ISP,
82
83 /* 24 */
84 PERIPH_ID_RESERVED24,
85 PERIPH_ID_RESERVED25,
86 PERIPH_ID_DISP2,
87 PERIPH_ID_DISP1,
88 PERIPH_ID_HOST1X,
89 PERIPH_ID_VCP,
90 PERIPH_ID_I2S0,
91 PERIPH_ID_CACHE2,
92
93 /* Middle word: 63:32 (DEVICES_H) */
94 PERIPH_ID_MEM,
95 PERIPH_ID_AHBDMA,
96 PERIPH_ID_APBDMA,
97 PERIPH_ID_RESERVED35,
98 PERIPH_ID_RESERVED36,
99 PERIPH_ID_STAT_MON,
100 PERIPH_ID_RESERVED38,
101 PERIPH_ID_FUSE,
102
103 /* 40 */
104 PERIPH_ID_KFUSE,
105 PERIPH_ID_SBC1,
106 PERIPH_ID_SNOR,
107 PERIPH_ID_RESERVED43,
108 PERIPH_ID_SBC2,
109 PERIPH_ID_XIO,
110 PERIPH_ID_SBC3,
111 PERIPH_ID_I2C5,
112
113 /* 48 */
114 PERIPH_ID_DSI,
115 PERIPH_ID_RESERVED49,
116 PERIPH_ID_HSI,
117 PERIPH_ID_HDMI,
118 PERIPH_ID_CSI,
119 PERIPH_ID_RESERVED53,
120 PERIPH_ID_I2C2,
121 PERIPH_ID_UART3,
122
123 /* 56 */
124 PERIPH_ID_MIPI_CAL,
125 PERIPH_ID_EMC,
126 PERIPH_ID_USB2,
127 PERIPH_ID_USB3,
128 PERIPH_ID_RESERVED60,
129 PERIPH_ID_VDE,
130 PERIPH_ID_BSEA,
131 PERIPH_ID_BSEV,
132
133 /* Upper word 95:64 (DEVICES_U) */
134 PERIPH_ID_RESERVED64,
135 PERIPH_ID_UART4,
136 PERIPH_ID_UART5,
137 PERIPH_ID_I2C3,
138 PERIPH_ID_SBC4,
139 PERIPH_ID_SDMMC3,
140 PERIPH_ID_PCIE,
141 PERIPH_ID_OWR,
142
143 /* 72 */
144 PERIPH_ID_AFI,
145 PERIPH_ID_CORESIGHT,
146 PERIPH_ID_PCIEXCLK,
147 PERIPH_ID_AVPUCQ,
148 PERIPH_ID_LA,
149 PERIPH_ID_TRACECLKIN,
150 PERIPH_ID_SOC_THERM,
151 PERIPH_ID_DTV,
152
153 /* 80 */
154 PERIPH_ID_RESERVED80,
155 PERIPH_ID_I2CSLOW,
156 PERIPH_ID_DSIB,
157 PERIPH_ID_TSEC,
158 PERIPH_ID_RESERVED84,
159 PERIPH_ID_RESERVED85,
160 PERIPH_ID_RESERVED86,
161 PERIPH_ID_EMUCIF,
162
163 /* 88 */
164 PERIPH_ID_RESERVED88,
165 PERIPH_ID_XUSB_HOST,
166 PERIPH_ID_RESERVED90,
167 PERIPH_ID_MSENC,
168 PERIPH_ID_RESERVED92,
169 PERIPH_ID_RESERVED93,
170 PERIPH_ID_RESERVED94,
171 PERIPH_ID_XUSB_DEV,
172
173 PERIPH_ID_VW_FIRST,
174 /* V word: 31:0 */
175 PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
176 PERIPH_ID_CPULP,
177 PERIPH_ID_V_RESERVED2,
178 PERIPH_ID_MSELECT,
179 PERIPH_ID_V_RESERVED4,
180 PERIPH_ID_I2S3,
181 PERIPH_ID_I2S4,
182 PERIPH_ID_I2C4,
183
184 /* 104 */
185 PERIPH_ID_SBC5,
186 PERIPH_ID_SBC6,
187 PERIPH_ID_AUDIO,
188 PERIPH_ID_APBIF,
189 PERIPH_ID_DAM0,
190 PERIPH_ID_DAM1,
191 PERIPH_ID_DAM2,
192 PERIPH_ID_HDA2CODEC2X,
193
194 /* 112 */
195 PERIPH_ID_ATOMICS,
196 PERIPH_ID_V_RESERVED17,
197 PERIPH_ID_V_RESERVED18,
198 PERIPH_ID_V_RESERVED19,
199 PERIPH_ID_V_RESERVED20,
200 PERIPH_ID_V_RESERVED21,
201 PERIPH_ID_V_RESERVED22,
202 PERIPH_ID_ACTMON,
203
204 /* 120 */
205 PERIPH_ID_EXTPERIPH1,
206 PERIPH_ID_EXTPERIPH2,
207 PERIPH_ID_EXTPERIPH3,
208 PERIPH_ID_OOB,
209 PERIPH_ID_SATA,
210 PERIPH_ID_HDA,
211 PERIPH_ID_V_RESERVED30,
212 PERIPH_ID_V_RESERVED31,
213
214 /* W word: 31:0 */
215 PERIPH_ID_HDA2HDMICODEC,
216 PERIPH_ID_SATACOLD,
217 PERIPH_ID_W_RESERVED2,
218 PERIPH_ID_W_RESERVED3,
219 PERIPH_ID_W_RESERVED4,
220 PERIPH_ID_W_RESERVED5,
221 PERIPH_ID_W_RESERVED6,
222 PERIPH_ID_W_RESERVED7,
223
224 /* 136 */
225 PERIPH_ID_CEC,
226 PERIPH_ID_W_RESERVED9,
227 PERIPH_ID_W_RESERVED10,
228 PERIPH_ID_W_RESERVED11,
229 PERIPH_ID_W_RESERVED12,
230 PERIPH_ID_W_RESERVED13,
231 PERIPH_ID_XUSB_PADCTL,
232 PERIPH_ID_W_RESERVED15,
233
234 /* 144 */
235 PERIPH_ID_W_RESERVED16,
236 PERIPH_ID_W_RESERVED17,
237 PERIPH_ID_W_RESERVED18,
238 PERIPH_ID_W_RESERVED19,
239 PERIPH_ID_W_RESERVED20,
240 PERIPH_ID_ENTROPY,
241 PERIPH_ID_DDS,
242 PERIPH_ID_W_RESERVED23,
243
244 /* 152 */
245 PERIPH_ID_DP2,
246 PERIPH_ID_AMX0,
247 PERIPH_ID_ADX0,
248 PERIPH_ID_DVFS,
249 PERIPH_ID_XUSB_SS,
250 PERIPH_ID_W_RESERVED29,
251 PERIPH_ID_W_RESERVED30,
252 PERIPH_ID_W_RESERVED31,
253
254 PERIPH_ID_X_FIRST,
255 /* X word: 31:0 */
256 PERIPH_ID_SPARE = PERIPH_ID_X_FIRST,
257 PERIPH_ID_X_RESERVED1,
258 PERIPH_ID_X_RESERVED2,
259 PERIPH_ID_X_RESERVED3,
260 PERIPH_ID_CAM_MCLK,
261 PERIPH_ID_CAM_MCLK2,
262 PERIPH_ID_I2C6,
263 PERIPH_ID_X_RESERVED7,
264
265 /* 168 */
266 PERIPH_ID_X_RESERVED8,
267 PERIPH_ID_X_RESERVED9,
268 PERIPH_ID_X_RESERVED10,
269 PERIPH_ID_VIM2_CLK,
270 PERIPH_ID_X_RESERVED12,
271 PERIPH_ID_X_RESERVED13,
272 PERIPH_ID_EMC_DLL,
273 PERIPH_ID_X_RESERVED15,
274
275 /* 176 */
276 PERIPH_ID_HDMI_AUDIO,
277 PERIPH_ID_CLK72MHZ,
278 PERIPH_ID_VIC,
279 PERIPH_ID_X_RESERVED19,
280 PERIPH_ID_ADX1,
281 PERIPH_ID_DPAUX,
282 PERIPH_ID_SOR0,
283 PERIPH_ID_X_RESERVED23,
284
285 /* 184 */
286 PERIPH_ID_GPU,
287 PERIPH_ID_AMX1,
288 PERIPH_ID_X_RESERVED26,
289 PERIPH_ID_X_RESERVED27,
290 PERIPH_ID_X_RESERVED28,
291 PERIPH_ID_X_RESERVED29,
292 PERIPH_ID_X_RESERVED30,
293 PERIPH_ID_X_RESERVED31,
294
295 PERIPH_ID_COUNT,
296 PERIPH_ID_NONE = -1,
297};
298
299enum pll_out_id {
300 PLL_OUT1,
301 PLL_OUT2,
302 PLL_OUT3,
303 PLL_OUT4
304};
305
306/*
307 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
308 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
309 * confusion bewteen PERIPH_ID_... and PERIPHC_...
310 *
311 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
312 * confusing.
313 */
314enum periphc_internal_id {
315 /* 0x00 */
316 PERIPHC_I2S1,
317 PERIPHC_I2S2,
318 PERIPHC_SPDIF_OUT,
319 PERIPHC_SPDIF_IN,
320 PERIPHC_PWM,
321 PERIPHC_05h,
322 PERIPHC_SBC2,
323 PERIPHC_SBC3,
324
325 /* 0x08 */
326 PERIPHC_08h,
327 PERIPHC_I2C1,
328 PERIPHC_I2C5,
329 PERIPHC_0bh,
330 PERIPHC_0ch,
331 PERIPHC_SBC1,
332 PERIPHC_DISP1,
333 PERIPHC_DISP2,
334
335 /* 0x10 */
336 PERIPHC_10h,
337 PERIPHC_11h,
338 PERIPHC_VI,
339 PERIPHC_13h,
340 PERIPHC_SDMMC1,
341 PERIPHC_SDMMC2,
342 PERIPHC_G3D,
343 PERIPHC_G2D,
344
345 /* 0x18 */
346 PERIPHC_18h,
347 PERIPHC_SDMMC4,
348 PERIPHC_VFIR,
349 PERIPHC_1Bh,
350 PERIPHC_1Ch,
351 PERIPHC_HSI,
352 PERIPHC_UART1,
353 PERIPHC_UART2,
354
355 /* 0x20 */
356 PERIPHC_HOST1X,
357 PERIPHC_21h,
358 PERIPHC_22h,
359 PERIPHC_HDMI,
360 PERIPHC_24h,
361 PERIPHC_25h,
362 PERIPHC_I2C2,
363 PERIPHC_EMC,
364
365 /* 0x28 */
366 PERIPHC_UART3,
367 PERIPHC_29h,
368 PERIPHC_VI_SENSOR,
369 PERIPHC_2bh,
370 PERIPHC_2ch,
371 PERIPHC_SBC4,
372 PERIPHC_I2C3,
373 PERIPHC_SDMMC3,
374
375 /* 0x30 */
376 PERIPHC_UART4,
377 PERIPHC_UART5,
378 PERIPHC_VDE,
379 PERIPHC_OWR,
380 PERIPHC_NOR,
381 PERIPHC_CSITE,
382 PERIPHC_I2S0,
383 PERIPHC_DTV,
384
385 /* 0x38 */
386 PERIPHC_38h,
387 PERIPHC_39h,
388 PERIPHC_3ah,
389 PERIPHC_3bh,
390 PERIPHC_MSENC,
391 PERIPHC_TSEC,
392 PERIPHC_3eh,
393 PERIPHC_OSC,
394
395 PERIPHC_VW_FIRST,
396 /* 0x40 */
397 PERIPHC_40h = PERIPHC_VW_FIRST,
398 PERIPHC_MSELECT,
399 PERIPHC_TSENSOR,
400 PERIPHC_I2S3,
401 PERIPHC_I2S4,
402 PERIPHC_I2C4,
403 PERIPHC_SBC5,
404 PERIPHC_SBC6,
405
406 /* 0x48 */
407 PERIPHC_AUDIO,
408 PERIPHC_49h,
409 PERIPHC_DAM0,
410 PERIPHC_DAM1,
411 PERIPHC_DAM2,
412 PERIPHC_HDA2CODEC2X,
413 PERIPHC_ACTMON,
414 PERIPHC_EXTPERIPH1,
415
416 /* 0x50 */
417 PERIPHC_EXTPERIPH2,
418 PERIPHC_EXTPERIPH3,
419 PERIPHC_52h,
420 PERIPHC_I2CSLOW,
421 PERIPHC_SYS,
422 PERIPHC_55h,
423 PERIPHC_56h,
424 PERIPHC_57h,
425
426 /* 0x58 */
427 PERIPHC_58h,
Simon Glass96e82a22015-04-14 21:03:34 -0600[diff] [blame]428 PERIPHC_SOR,
Tom Warren999c6ba2014-01-24 12:46:13 -0700[diff] [blame]429 PERIPHC_5ah,
430 PERIPHC_5bh,
431 PERIPHC_SATAOOB,
432 PERIPHC_SATA,
433 PERIPHC_HDA, /* 0x428 */
434 PERIPHC_5fh,
435
436 PERIPHC_X_FIRST,
437 /* 0x60 */
438 PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */
439 PERIPHC_XUSB_FALCON,
440 PERIPHC_XUSB_FS,
441 PERIPHC_XUSB_CORE_DEV,
442 PERIPHC_XUSB_SS,
443 PERIPHC_CILAB,
444 PERIPHC_CILCD,
445 PERIPHC_CILE,
446
447 /* 0x68 */
448 PERIPHC_DSIA_LP,
449 PERIPHC_DSIB_LP,
450 PERIPHC_ENTROPY,
451 PERIPHC_DVFS_REF,
452 PERIPHC_DVFS_SOC,
453 PERIPHC_TRACECLKIN,
454 PERIPHC_ADX0,
455 PERIPHC_AMX0,
456
457 /* 0x70 */
458 PERIPHC_EMC_LATENCY,
459 PERIPHC_SOC_THERM,
460 PERIPHC_72h,
461 PERIPHC_73h,
462 PERIPHC_74h,
463 PERIPHC_75h,
464 PERIPHC_VI_SENSOR2,
465 PERIPHC_I2C6,
466
467 /* 0x78 */
468 PERIPHC_78h,
469 PERIPHC_EMC_DLL,
470 PERIPHC_HDMI_AUDIO,
471 PERIPHC_CLK72MHZ,
472 PERIPHC_ADX1,
473 PERIPHC_AMX1,
474 PERIPHC_VIC,
475 PERIPHC_7fh,
476
477 PERIPHC_COUNT,
478
479 PERIPHC_NONE = -1,
480};
481
482/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
483#define PERIPH_REG(id) \
484 (id < PERIPH_ID_VW_FIRST) ? \
485 ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
486
487/* Mask value for a clock (within PERIPH_REG(id)) */
488#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
489
490/* return 1 if a PLL ID is in range */
491#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
492
493/* return 1 if a peripheral ID is in range */
494#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
495 (id) < PERIPH_ID_COUNT)
496
497#endif /* _TEGRA124_CLOCK_TABLES_H_ */