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Roy Zang111fd192012-10-08 07:44:21 +00001/*
2 * Copyright 2012 Freescale Semiconductor, Inc.
Andy Flemingb21f87a32014-07-25 17:39:08 -05003 * Andy Fleming <afleming@gmail.com>
Roy Zang111fd192012-10-08 07:44:21 +00004 * Roy Zang <tie-fei.zang@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Roy Zang111fd192012-10-08 07:44:21 +00007 * Some part is taken from tsec.c
8 */
9#include <common.h>
10#include <miiphy.h>
11#include <phy.h>
12#include <asm/io.h>
Shaohui Xiecd348ef2015-03-20 19:28:19 -070013#include <fsl_memac.h>
Roy Zang111fd192012-10-08 07:44:21 +000014#include <fm_eth.h>
15
Shaohui Xiecd348ef2015-03-20 19:28:19 -070016#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
17#define memac_out_32(a, v) out_le32(a, v)
18#define memac_clrbits_32(a, v) clrbits_le32(a, v)
19#define memac_setbits_32(a, v) setbits_le32(a, v)
20#else
21#define memac_out_32(a, v) out_be32(a, v)
22#define memac_clrbits_32(a, v) clrbits_be32(a, v)
23#define memac_setbits_32(a, v) setbits_be32(a, v)
24#endif
25
26static u32 memac_in_32(u32 *reg)
27{
28#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
29 return in_le32(reg);
30#else
31 return in_be32(reg);
32#endif
33}
34
Roy Zang111fd192012-10-08 07:44:21 +000035/*
36 * Write value to the PHY for this device to the register at regnum, waiting
37 * until the write is done before it returns. All PHY configuration has to be
38 * done through the TSEC1 MIIM regs
39 */
40int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
41 int regnum, u16 value)
42{
43 u32 mdio_ctl;
44 struct memac_mdio_controller *regs = bus->priv;
45 u32 c45 = 1; /* Default to 10G interface */
46
47 if (dev_addr == MDIO_DEVAD_NONE) {
48 c45 = 0; /* clause 22 */
49 dev_addr = regnum & 0x1f;
Shaohui Xiecd348ef2015-03-20 19:28:19 -070050 memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
Shaohui Xie3a7ed5a2014-04-22 18:21:37 +080051 } else
Shaohui Xiecd348ef2015-03-20 19:28:19 -070052 memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
Roy Zang111fd192012-10-08 07:44:21 +000053
54 /* Wait till the bus is free */
Shaohui Xiecd348ef2015-03-20 19:28:19 -070055 while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
Roy Zang111fd192012-10-08 07:44:21 +000056 ;
57
58 /* Set the port and dev addr */
59 mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
Shaohui Xiecd348ef2015-03-20 19:28:19 -070060 memac_out_32(&regs->mdio_ctl, mdio_ctl);
Roy Zang111fd192012-10-08 07:44:21 +000061
62 /* Set the register address */
63 if (c45)
Shaohui Xiecd348ef2015-03-20 19:28:19 -070064 memac_out_32(&regs->mdio_addr, regnum & 0xffff);
Roy Zang111fd192012-10-08 07:44:21 +000065
66 /* Wait till the bus is free */
Shaohui Xiecd348ef2015-03-20 19:28:19 -070067 while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
Roy Zang111fd192012-10-08 07:44:21 +000068 ;
69
70 /* Write the value to the register */
Shaohui Xiecd348ef2015-03-20 19:28:19 -070071 memac_out_32(&regs->mdio_data, MDIO_DATA(value));
Roy Zang111fd192012-10-08 07:44:21 +000072
73 /* Wait till the MDIO write is complete */
Shaohui Xiecd348ef2015-03-20 19:28:19 -070074 while ((memac_in_32(&regs->mdio_data)) & MDIO_DATA_BSY)
Roy Zang111fd192012-10-08 07:44:21 +000075 ;
76
77 return 0;
78}
79
80/*
81 * Reads from register regnum in the PHY for device dev, returning the value.
82 * Clears miimcom first. All PHY configuration has to be done through the
83 * TSEC1 MIIM regs
84 */
85int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
86 int regnum)
87{
88 u32 mdio_ctl;
89 struct memac_mdio_controller *regs = bus->priv;
90 u32 c45 = 1;
91
92 if (dev_addr == MDIO_DEVAD_NONE) {
Shaohui Xieff5fb2a2014-08-13 18:32:19 +080093 if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME))
94 return 0xffff;
Roy Zang111fd192012-10-08 07:44:21 +000095 c45 = 0; /* clause 22 */
96 dev_addr = regnum & 0x1f;
Shaohui Xiecd348ef2015-03-20 19:28:19 -070097 memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
Shaohui Xie3a7ed5a2014-04-22 18:21:37 +080098 } else
Shaohui Xiecd348ef2015-03-20 19:28:19 -070099 memac_setbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
Roy Zang111fd192012-10-08 07:44:21 +0000100
101 /* Wait till the bus is free */
Shaohui Xiecd348ef2015-03-20 19:28:19 -0700102 while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
Roy Zang111fd192012-10-08 07:44:21 +0000103 ;
104
105 /* Set the Port and Device Addrs */
106 mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
Shaohui Xiecd348ef2015-03-20 19:28:19 -0700107 memac_out_32(&regs->mdio_ctl, mdio_ctl);
Roy Zang111fd192012-10-08 07:44:21 +0000108
109 /* Set the register address */
110 if (c45)
Shaohui Xiecd348ef2015-03-20 19:28:19 -0700111 memac_out_32(&regs->mdio_addr, regnum & 0xffff);
Roy Zang111fd192012-10-08 07:44:21 +0000112
113 /* Wait till the bus is free */
Shaohui Xiecd348ef2015-03-20 19:28:19 -0700114 while ((memac_in_32(&regs->mdio_stat)) & MDIO_STAT_BSY)
Roy Zang111fd192012-10-08 07:44:21 +0000115 ;
116
117 /* Initiate the read */
118 mdio_ctl |= MDIO_CTL_READ;
Shaohui Xiecd348ef2015-03-20 19:28:19 -0700119 memac_out_32(&regs->mdio_ctl, mdio_ctl);
Roy Zang111fd192012-10-08 07:44:21 +0000120
121 /* Wait till the MDIO write is complete */
Shaohui Xiecd348ef2015-03-20 19:28:19 -0700122 while ((memac_in_32(&regs->mdio_data)) & MDIO_DATA_BSY)
Roy Zang111fd192012-10-08 07:44:21 +0000123 ;
124
125 /* Return all Fs if nothing was there */
Shaohui Xiecd348ef2015-03-20 19:28:19 -0700126 if (memac_in_32(&regs->mdio_stat) & MDIO_STAT_RD_ER)
Roy Zang111fd192012-10-08 07:44:21 +0000127 return 0xffff;
128
Shaohui Xiecd348ef2015-03-20 19:28:19 -0700129 return memac_in_32(&regs->mdio_data) & 0xffff;
Roy Zang111fd192012-10-08 07:44:21 +0000130}
131
132int memac_mdio_reset(struct mii_dev *bus)
133{
134 return 0;
135}
136
137int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info)
138{
139 struct mii_dev *bus = mdio_alloc();
140
141 if (!bus) {
142 printf("Failed to allocate FM TGEC MDIO bus\n");
143 return -1;
144 }
145
146 bus->read = memac_mdio_read;
147 bus->write = memac_mdio_write;
148 bus->reset = memac_mdio_reset;
149 sprintf(bus->name, info->name);
150
151 bus->priv = info->regs;
152
Priyanka Jain2ee6c522014-04-08 10:55:49 +0530153 /*
154 * On some platforms like B4860, default value of MDIO_CLK_DIV bits
155 * in mdio_stat(mdio_cfg) register generates MDIO clock too high
156 * (much higher than 2.5MHz), violating the IEEE specs.
157 * On other platforms like T1040, default value of MDIO_CLK_DIV bits
158 * is zero, so MDIO clock is disabled.
159 * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
160 * be properly initialized.
Shaohui Xieae6b4582014-08-13 18:38:09 +0800161 * NEG bit default should be '1' as per FMAN-v3 RM, but on platform
162 * like T2080QDS, this bit default is '0', which leads to MDIO failure
163 * on XAUI PHY, so set this bit definitely.
Priyanka Jain2ee6c522014-04-08 10:55:49 +0530164 */
Shaohui Xiecd348ef2015-03-20 19:28:19 -0700165 memac_setbits_32(
166 &((struct memac_mdio_controller *)info->regs)->mdio_stat,
167 MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
Priyanka Jain2ee6c522014-04-08 10:55:49 +0530168
Roy Zang111fd192012-10-08 07:44:21 +0000169 return mdio_register(bus);
170}