blob: 1cd1e409e3eeaa11ce99adab149c648a576e5c60 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glassff3e0772015-03-05 12:25:25 -07002/*
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
Simon Glassff3e0772015-03-05 12:25:25 -07005 */
6
7#include <common.h>
8#include <dm.h>
9#include <errno.h>
Simon Glassff3e0772015-03-05 12:25:25 -070010#include <inttypes.h>
11#include <pci.h>
Simon Glass21d1fe72015-11-29 13:18:03 -070012#include <asm/io.h>
Simon Glassff3e0772015-03-05 12:25:25 -070013#include <dm/device-internal.h>
Simon Glassbf501592017-05-18 20:09:51 -060014#include <dm/lists.h>
Bin Meng348b7442015-08-20 06:40:23 -070015#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
16#include <asm/fsp/fsp_support.h>
17#endif
Simon Glass5e23b8b2015-11-29 13:17:49 -070018#include "pci_internal.h"
Simon Glassff3e0772015-03-05 12:25:25 -070019
20DECLARE_GLOBAL_DATA_PTR;
21
Simon Glassa6eb93b2016-01-18 20:19:14 -070022int pci_get_bus(int busnum, struct udevice **busp)
Simon Glass983c6ba22015-08-31 18:55:35 -060023{
24 int ret;
25
26 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
27
28 /* Since buses may not be numbered yet try a little harder with bus 0 */
29 if (ret == -ENODEV) {
Simon Glass3f603cb2016-02-11 13:23:26 -070030 ret = uclass_first_device_err(UCLASS_PCI, busp);
Simon Glass983c6ba22015-08-31 18:55:35 -060031 if (ret)
32 return ret;
Simon Glass983c6ba22015-08-31 18:55:35 -060033 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
34 }
35
36 return ret;
37}
38
Simon Glass9f60fb02015-11-19 20:27:00 -070039struct udevice *pci_get_controller(struct udevice *dev)
40{
41 while (device_is_on_pci_bus(dev))
42 dev = dev->parent;
43
44 return dev;
45}
46
Simon Glass21ccce12015-11-29 13:17:47 -070047pci_dev_t dm_pci_get_bdf(struct udevice *dev)
Simon Glass4b515e42015-07-06 16:47:46 -060048{
49 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
50 struct udevice *bus = dev->parent;
51
52 return PCI_ADD_BUS(bus->seq, pplat->devfn);
53}
54
Simon Glassff3e0772015-03-05 12:25:25 -070055/**
56 * pci_get_bus_max() - returns the bus number of the last active bus
57 *
58 * @return last bus number, or -1 if no active buses
59 */
60static int pci_get_bus_max(void)
61{
62 struct udevice *bus;
63 struct uclass *uc;
64 int ret = -1;
65
66 ret = uclass_get(UCLASS_PCI, &uc);
67 uclass_foreach_dev(bus, uc) {
68 if (bus->seq > ret)
69 ret = bus->seq;
70 }
71
72 debug("%s: ret=%d\n", __func__, ret);
73
74 return ret;
75}
76
77int pci_last_busno(void)
78{
Bin Meng069155c2015-10-01 00:36:01 -070079 return pci_get_bus_max();
Simon Glassff3e0772015-03-05 12:25:25 -070080}
81
82int pci_get_ff(enum pci_size_t size)
83{
84 switch (size) {
85 case PCI_SIZE_8:
86 return 0xff;
87 case PCI_SIZE_16:
88 return 0xffff;
89 default:
90 return 0xffffffff;
91 }
92}
93
94int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
95 struct udevice **devp)
96{
97 struct udevice *dev;
98
99 for (device_find_first_child(bus, &dev);
100 dev;
101 device_find_next_child(&dev)) {
102 struct pci_child_platdata *pplat;
103
104 pplat = dev_get_parent_platdata(dev);
105 if (pplat && pplat->devfn == find_devfn) {
106 *devp = dev;
107 return 0;
108 }
109 }
110
111 return -ENODEV;
112}
113
Simon Glassf3f1fae2015-11-29 13:17:48 -0700114int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
Simon Glassff3e0772015-03-05 12:25:25 -0700115{
116 struct udevice *bus;
117 int ret;
118
Simon Glass983c6ba22015-08-31 18:55:35 -0600119 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700120 if (ret)
121 return ret;
122 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
123}
124
125static int pci_device_matches_ids(struct udevice *dev,
126 struct pci_device_id *ids)
127{
128 struct pci_child_platdata *pplat;
129 int i;
130
131 pplat = dev_get_parent_platdata(dev);
132 if (!pplat)
133 return -EINVAL;
134 for (i = 0; ids[i].vendor != 0; i++) {
135 if (pplat->vendor == ids[i].vendor &&
136 pplat->device == ids[i].device)
137 return i;
138 }
139
140 return -EINVAL;
141}
142
143int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
144 int *indexp, struct udevice **devp)
145{
146 struct udevice *dev;
147
148 /* Scan all devices on this bus */
149 for (device_find_first_child(bus, &dev);
150 dev;
151 device_find_next_child(&dev)) {
152 if (pci_device_matches_ids(dev, ids) >= 0) {
153 if ((*indexp)-- <= 0) {
154 *devp = dev;
155 return 0;
156 }
157 }
158 }
159
160 return -ENODEV;
161}
162
163int pci_find_device_id(struct pci_device_id *ids, int index,
164 struct udevice **devp)
165{
166 struct udevice *bus;
167
168 /* Scan all known buses */
169 for (uclass_first_device(UCLASS_PCI, &bus);
170 bus;
171 uclass_next_device(&bus)) {
172 if (!pci_bus_find_devices(bus, ids, &index, devp))
173 return 0;
174 }
175 *devp = NULL;
176
177 return -ENODEV;
178}
179
Simon Glass5c0bf642015-11-29 13:17:50 -0700180static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
181 unsigned int device, int *indexp,
182 struct udevice **devp)
183{
184 struct pci_child_platdata *pplat;
185 struct udevice *dev;
186
187 for (device_find_first_child(bus, &dev);
188 dev;
189 device_find_next_child(&dev)) {
190 pplat = dev_get_parent_platdata(dev);
191 if (pplat->vendor == vendor && pplat->device == device) {
192 if (!(*indexp)--) {
193 *devp = dev;
194 return 0;
195 }
196 }
197 }
198
199 return -ENODEV;
200}
201
202int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
203 struct udevice **devp)
204{
205 struct udevice *bus;
206
207 /* Scan all known buses */
208 for (uclass_first_device(UCLASS_PCI, &bus);
209 bus;
210 uclass_next_device(&bus)) {
211 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
212 return device_probe(*devp);
213 }
214 *devp = NULL;
215
216 return -ENODEV;
217}
218
Simon Glassa0eb8352015-11-29 13:17:52 -0700219int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
220{
221 struct udevice *dev;
222
223 /* Scan all known buses */
224 for (pci_find_first_device(&dev);
225 dev;
226 pci_find_next_device(&dev)) {
227 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
228
229 if (pplat->class == find_class && !index--) {
230 *devp = dev;
231 return device_probe(*devp);
232 }
233 }
234 *devp = NULL;
235
236 return -ENODEV;
237}
238
Simon Glassff3e0772015-03-05 12:25:25 -0700239int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
240 unsigned long value, enum pci_size_t size)
241{
242 struct dm_pci_ops *ops;
243
244 ops = pci_get_ops(bus);
245 if (!ops->write_config)
246 return -ENOSYS;
247 return ops->write_config(bus, bdf, offset, value, size);
248}
249
Simon Glass319dba12016-03-06 19:27:52 -0700250int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
251 u32 clr, u32 set)
252{
253 ulong val;
254 int ret;
255
256 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
257 if (ret)
258 return ret;
259 val &= ~clr;
260 val |= set;
261
262 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
263}
264
Simon Glassff3e0772015-03-05 12:25:25 -0700265int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
266 enum pci_size_t size)
267{
268 struct udevice *bus;
269 int ret;
270
Simon Glass983c6ba22015-08-31 18:55:35 -0600271 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700272 if (ret)
273 return ret;
274
Bin Meng4d8615c2015-07-19 00:20:04 +0800275 return pci_bus_write_config(bus, bdf, offset, value, size);
Simon Glassff3e0772015-03-05 12:25:25 -0700276}
277
Simon Glass66afb4e2015-08-10 07:05:03 -0600278int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
279 enum pci_size_t size)
280{
281 struct udevice *bus;
282
Bin Meng1e0f2262015-09-11 03:24:34 -0700283 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass66afb4e2015-08-10 07:05:03 -0600284 bus = bus->parent;
Simon Glass21ccce12015-11-29 13:17:47 -0700285 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
286 size);
Simon Glass66afb4e2015-08-10 07:05:03 -0600287}
288
Simon Glassff3e0772015-03-05 12:25:25 -0700289int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
290{
291 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
292}
293
294int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
295{
296 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
297}
298
299int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
300{
301 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
302}
303
Simon Glass66afb4e2015-08-10 07:05:03 -0600304int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
305{
306 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
307}
308
309int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
310{
311 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
312}
313
314int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
315{
316 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
317}
318
Simon Glassff3e0772015-03-05 12:25:25 -0700319int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
320 unsigned long *valuep, enum pci_size_t size)
321{
322 struct dm_pci_ops *ops;
323
324 ops = pci_get_ops(bus);
325 if (!ops->read_config)
326 return -ENOSYS;
327 return ops->read_config(bus, bdf, offset, valuep, size);
328}
329
330int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
331 enum pci_size_t size)
332{
333 struct udevice *bus;
334 int ret;
335
Simon Glass983c6ba22015-08-31 18:55:35 -0600336 ret = pci_get_bus(PCI_BUS(bdf), &bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700337 if (ret)
338 return ret;
339
Bin Meng4d8615c2015-07-19 00:20:04 +0800340 return pci_bus_read_config(bus, bdf, offset, valuep, size);
Simon Glassff3e0772015-03-05 12:25:25 -0700341}
342
Simon Glass66afb4e2015-08-10 07:05:03 -0600343int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
344 enum pci_size_t size)
345{
346 struct udevice *bus;
347
Bin Meng1e0f2262015-09-11 03:24:34 -0700348 for (bus = dev; device_is_on_pci_bus(bus);)
Simon Glass66afb4e2015-08-10 07:05:03 -0600349 bus = bus->parent;
Simon Glass21ccce12015-11-29 13:17:47 -0700350 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
Simon Glass66afb4e2015-08-10 07:05:03 -0600351 size);
352}
353
Simon Glassff3e0772015-03-05 12:25:25 -0700354int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
355{
356 unsigned long value;
357 int ret;
358
359 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
360 if (ret)
361 return ret;
362 *valuep = value;
363
364 return 0;
365}
366
367int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
368{
369 unsigned long value;
370 int ret;
371
372 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
373 if (ret)
374 return ret;
375 *valuep = value;
376
377 return 0;
378}
379
380int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
381{
382 unsigned long value;
383 int ret;
384
385 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
386 if (ret)
387 return ret;
388 *valuep = value;
389
390 return 0;
391}
392
Simon Glass66afb4e2015-08-10 07:05:03 -0600393int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
394{
395 unsigned long value;
396 int ret;
397
398 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
399 if (ret)
400 return ret;
401 *valuep = value;
402
403 return 0;
404}
405
406int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
407{
408 unsigned long value;
409 int ret;
410
411 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
412 if (ret)
413 return ret;
414 *valuep = value;
415
416 return 0;
417}
418
419int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
420{
421 unsigned long value;
422 int ret;
423
424 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
425 if (ret)
426 return ret;
427 *valuep = value;
428
429 return 0;
430}
431
Simon Glass319dba12016-03-06 19:27:52 -0700432int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
433{
434 u8 val;
435 int ret;
436
437 ret = dm_pci_read_config8(dev, offset, &val);
438 if (ret)
439 return ret;
440 val &= ~clr;
441 val |= set;
442
443 return dm_pci_write_config8(dev, offset, val);
444}
445
446int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
447{
448 u16 val;
449 int ret;
450
451 ret = dm_pci_read_config16(dev, offset, &val);
452 if (ret)
453 return ret;
454 val &= ~clr;
455 val |= set;
456
457 return dm_pci_write_config16(dev, offset, val);
458}
459
460int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
461{
462 u32 val;
463 int ret;
464
465 ret = dm_pci_read_config32(dev, offset, &val);
466 if (ret)
467 return ret;
468 val &= ~clr;
469 val |= set;
470
471 return dm_pci_write_config32(dev, offset, val);
472}
473
Bin Mengbbbcb522015-10-01 00:36:02 -0700474static void set_vga_bridge_bits(struct udevice *dev)
475{
476 struct udevice *parent = dev->parent;
477 u16 bc;
478
479 while (parent->seq != 0) {
480 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
481 bc |= PCI_BRIDGE_CTL_VGA;
482 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
483 parent = parent->parent;
484 }
485}
486
Simon Glassff3e0772015-03-05 12:25:25 -0700487int pci_auto_config_devices(struct udevice *bus)
488{
489 struct pci_controller *hose = bus->uclass_priv;
Bin Mengbbbcb522015-10-01 00:36:02 -0700490 struct pci_child_platdata *pplat;
Simon Glassff3e0772015-03-05 12:25:25 -0700491 unsigned int sub_bus;
492 struct udevice *dev;
493 int ret;
494
495 sub_bus = bus->seq;
496 debug("%s: start\n", __func__);
497 pciauto_config_init(hose);
498 for (ret = device_find_first_child(bus, &dev);
499 !ret && dev;
500 ret = device_find_next_child(&dev)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700501 unsigned int max_bus;
Simon Glass4d214552015-09-08 17:52:47 -0600502 int ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700503
Simon Glassff3e0772015-03-05 12:25:25 -0700504 debug("%s: device %s\n", __func__, dev->name);
Simon Glass5e23b8b2015-11-29 13:17:49 -0700505 ret = dm_pciauto_config_device(dev);
Simon Glass4d214552015-09-08 17:52:47 -0600506 if (ret < 0)
507 return ret;
508 max_bus = ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700509 sub_bus = max(sub_bus, max_bus);
Bin Mengbbbcb522015-10-01 00:36:02 -0700510
511 pplat = dev_get_parent_platdata(dev);
512 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
513 set_vga_bridge_bits(dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700514 }
515 debug("%s: done\n", __func__);
516
517 return sub_bus;
518}
519
Tuomas Tynkkynenbadb9922017-09-19 23:18:03 +0300520int pci_generic_mmap_write_config(
521 struct udevice *bus,
522 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
523 pci_dev_t bdf,
524 uint offset,
525 ulong value,
526 enum pci_size_t size)
527{
528 void *address;
529
530 if (addr_f(bus, bdf, offset, &address) < 0)
531 return 0;
532
533 switch (size) {
534 case PCI_SIZE_8:
535 writeb(value, address);
536 return 0;
537 case PCI_SIZE_16:
538 writew(value, address);
539 return 0;
540 case PCI_SIZE_32:
541 writel(value, address);
542 return 0;
543 default:
544 return -EINVAL;
545 }
546}
547
548int pci_generic_mmap_read_config(
549 struct udevice *bus,
550 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
551 pci_dev_t bdf,
552 uint offset,
553 ulong *valuep,
554 enum pci_size_t size)
555{
556 void *address;
557
558 if (addr_f(bus, bdf, offset, &address) < 0) {
559 *valuep = pci_get_ff(size);
560 return 0;
561 }
562
563 switch (size) {
564 case PCI_SIZE_8:
565 *valuep = readb(address);
566 return 0;
567 case PCI_SIZE_16:
568 *valuep = readw(address);
569 return 0;
570 case PCI_SIZE_32:
571 *valuep = readl(address);
572 return 0;
573 default:
574 return -EINVAL;
575 }
576}
577
Simon Glass5e23b8b2015-11-29 13:17:49 -0700578int dm_pci_hose_probe_bus(struct udevice *bus)
Simon Glassff3e0772015-03-05 12:25:25 -0700579{
Simon Glassff3e0772015-03-05 12:25:25 -0700580 int sub_bus;
581 int ret;
582
583 debug("%s\n", __func__);
Simon Glassff3e0772015-03-05 12:25:25 -0700584
585 sub_bus = pci_get_bus_max() + 1;
586 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
Simon Glass5e23b8b2015-11-29 13:17:49 -0700587 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700588
589 ret = device_probe(bus);
590 if (ret) {
Simon Glass3129ace2015-09-08 17:52:48 -0600591 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
Simon Glassff3e0772015-03-05 12:25:25 -0700592 ret);
593 return ret;
594 }
595 if (sub_bus != bus->seq) {
596 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
597 __func__, bus->name, bus->seq, sub_bus);
598 return -EPIPE;
599 }
600 sub_bus = pci_get_bus_max();
Simon Glass5e23b8b2015-11-29 13:17:49 -0700601 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
Simon Glassff3e0772015-03-05 12:25:25 -0700602
603 return sub_bus;
604}
605
Simon Glassaba92962015-07-06 16:47:44 -0600606/**
607 * pci_match_one_device - Tell if a PCI device structure has a matching
608 * PCI device id structure
609 * @id: single PCI device id structure to match
Hou Zhiqiang0367bd42017-03-22 16:07:24 +0800610 * @find: the PCI device id structure to match against
Simon Glassaba92962015-07-06 16:47:44 -0600611 *
Hou Zhiqiang0367bd42017-03-22 16:07:24 +0800612 * Returns true if the finding pci_device_id structure matched or false if
613 * there is no match.
Simon Glassaba92962015-07-06 16:47:44 -0600614 */
615static bool pci_match_one_id(const struct pci_device_id *id,
616 const struct pci_device_id *find)
617{
618 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
619 (id->device == PCI_ANY_ID || id->device == find->device) &&
620 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
621 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
622 !((id->class ^ find->class) & id->class_mask))
623 return true;
624
625 return false;
626}
627
628/**
629 * pci_find_and_bind_driver() - Find and bind the right PCI driver
630 *
631 * This only looks at certain fields in the descriptor.
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600632 *
633 * @parent: Parent bus
634 * @find_id: Specification of the driver to find
635 * @bdf: Bus/device/function addreess - see PCI_BDF()
636 * @devp: Returns a pointer to the device created
637 * @return 0 if OK, -EPERM if the device is not needed before relocation and
638 * therefore was not created, other -ve value on error
Simon Glassaba92962015-07-06 16:47:44 -0600639 */
640static int pci_find_and_bind_driver(struct udevice *parent,
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600641 struct pci_device_id *find_id,
642 pci_dev_t bdf, struct udevice **devp)
Simon Glassaba92962015-07-06 16:47:44 -0600643{
644 struct pci_driver_entry *start, *entry;
645 const char *drv;
646 int n_ents;
647 int ret;
648 char name[30], *str;
Bin Meng08fc7b82015-08-20 06:40:17 -0700649 bool bridge;
Simon Glassaba92962015-07-06 16:47:44 -0600650
651 *devp = NULL;
652
653 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
654 find_id->vendor, find_id->device);
655 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
656 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
657 for (entry = start; entry != start + n_ents; entry++) {
658 const struct pci_device_id *id;
659 struct udevice *dev;
660 const struct driver *drv;
661
662 for (id = entry->match;
663 id->vendor || id->subvendor || id->class_mask;
664 id++) {
665 if (!pci_match_one_id(id, find_id))
666 continue;
667
668 drv = entry->driver;
Bin Meng08fc7b82015-08-20 06:40:17 -0700669
670 /*
671 * In the pre-relocation phase, we only bind devices
672 * whose driver has the DM_FLAG_PRE_RELOC set, to save
673 * precious memory space as on some platforms as that
674 * space is pretty limited (ie: using Cache As RAM).
675 */
676 if (!(gd->flags & GD_FLG_RELOC) &&
677 !(drv->flags & DM_FLAG_PRE_RELOC))
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600678 return -EPERM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700679
Simon Glassaba92962015-07-06 16:47:44 -0600680 /*
681 * We could pass the descriptor to the driver as
682 * platdata (instead of NULL) and allow its bind()
683 * method to return -ENOENT if it doesn't support this
684 * device. That way we could continue the search to
685 * find another driver. For now this doesn't seem
686 * necesssary, so just bind the first match.
687 */
688 ret = device_bind(parent, drv, drv->name, NULL, -1,
689 &dev);
690 if (ret)
691 goto error;
692 debug("%s: Match found: %s\n", __func__, drv->name);
693 dev->driver_data = find_id->driver_data;
694 *devp = dev;
695 return 0;
696 }
697 }
698
Bin Meng08fc7b82015-08-20 06:40:17 -0700699 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
700 /*
701 * In the pre-relocation phase, we only bind bridge devices to save
702 * precious memory space as on some platforms as that space is pretty
703 * limited (ie: using Cache As RAM).
704 */
705 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600706 return -EPERM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700707
Simon Glassaba92962015-07-06 16:47:44 -0600708 /* Bind a generic driver so that the device can be used */
Bin Meng4d8615c2015-07-19 00:20:04 +0800709 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
710 PCI_FUNC(bdf));
Simon Glassaba92962015-07-06 16:47:44 -0600711 str = strdup(name);
712 if (!str)
713 return -ENOMEM;
Bin Meng08fc7b82015-08-20 06:40:17 -0700714 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
715
Simon Glassaba92962015-07-06 16:47:44 -0600716 ret = device_bind_driver(parent, drv, str, devp);
717 if (ret) {
Simon Glass3129ace2015-09-08 17:52:48 -0600718 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
xypron.glpk@gmx.dec42640c2017-05-08 20:40:16 +0200719 free(str);
Simon Glassaba92962015-07-06 16:47:44 -0600720 return ret;
721 }
722 debug("%s: No match found: bound generic driver instead\n", __func__);
723
724 return 0;
725
726error:
727 debug("%s: No match found: error %d\n", __func__, ret);
728 return ret;
729}
730
Simon Glassff3e0772015-03-05 12:25:25 -0700731int pci_bind_bus_devices(struct udevice *bus)
732{
733 ulong vendor, device;
734 ulong header_type;
Bin Meng4d8615c2015-07-19 00:20:04 +0800735 pci_dev_t bdf, end;
Simon Glassff3e0772015-03-05 12:25:25 -0700736 bool found_multi;
737 int ret;
738
739 found_multi = false;
Bin Meng4d8615c2015-07-19 00:20:04 +0800740 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
741 PCI_MAX_PCI_FUNCTIONS - 1);
Yoshinori Sato6d9f5b02016-04-25 15:41:01 +0900742 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
Bin Meng4d8615c2015-07-19 00:20:04 +0800743 bdf += PCI_BDF(0, 0, 1)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700744 struct pci_child_platdata *pplat;
745 struct udevice *dev;
746 ulong class;
747
Bin Meng4d8615c2015-07-19 00:20:04 +0800748 if (PCI_FUNC(bdf) && !found_multi)
Simon Glassff3e0772015-03-05 12:25:25 -0700749 continue;
750 /* Check only the first access, we don't expect problems */
Bin Meng4d8615c2015-07-19 00:20:04 +0800751 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
Simon Glassff3e0772015-03-05 12:25:25 -0700752 &header_type, PCI_SIZE_8);
753 if (ret)
754 goto error;
Bin Meng4d8615c2015-07-19 00:20:04 +0800755 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
Simon Glassff3e0772015-03-05 12:25:25 -0700756 PCI_SIZE_16);
757 if (vendor == 0xffff || vendor == 0x0000)
758 continue;
759
Bin Meng4d8615c2015-07-19 00:20:04 +0800760 if (!PCI_FUNC(bdf))
Simon Glassff3e0772015-03-05 12:25:25 -0700761 found_multi = header_type & 0x80;
762
763 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
Bin Meng4d8615c2015-07-19 00:20:04 +0800764 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
765 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
Simon Glassff3e0772015-03-05 12:25:25 -0700766 PCI_SIZE_16);
Bin Meng4d8615c2015-07-19 00:20:04 +0800767 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
Simon Glassaba92962015-07-06 16:47:44 -0600768 PCI_SIZE_32);
769 class >>= 8;
Simon Glassff3e0772015-03-05 12:25:25 -0700770
771 /* Find this device in the device tree */
Bin Meng4d8615c2015-07-19 00:20:04 +0800772 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700773
Simon Glass8bd42522015-11-29 13:18:09 -0700774 /* If nothing in the device tree, bind a device */
Simon Glassff3e0772015-03-05 12:25:25 -0700775 if (ret == -ENODEV) {
Simon Glassaba92962015-07-06 16:47:44 -0600776 struct pci_device_id find_id;
777 ulong val;
Simon Glassff3e0772015-03-05 12:25:25 -0700778
Simon Glassaba92962015-07-06 16:47:44 -0600779 memset(&find_id, '\0', sizeof(find_id));
780 find_id.vendor = vendor;
781 find_id.device = device;
782 find_id.class = class;
783 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
Bin Meng4d8615c2015-07-19 00:20:04 +0800784 pci_bus_read_config(bus, bdf,
Simon Glassaba92962015-07-06 16:47:44 -0600785 PCI_SUBSYSTEM_VENDOR_ID,
786 &val, PCI_SIZE_32);
787 find_id.subvendor = val & 0xffff;
788 find_id.subdevice = val >> 16;
789 }
Bin Meng4d8615c2015-07-19 00:20:04 +0800790 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
Simon Glassaba92962015-07-06 16:47:44 -0600791 &dev);
Simon Glassff3e0772015-03-05 12:25:25 -0700792 }
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600793 if (ret == -EPERM)
794 continue;
795 else if (ret)
Simon Glassff3e0772015-03-05 12:25:25 -0700796 return ret;
797
798 /* Update the platform data */
Simon Glass5dbcf3a2015-09-08 17:52:49 -0600799 pplat = dev_get_parent_platdata(dev);
800 pplat->devfn = PCI_MASK_BUS(bdf);
801 pplat->vendor = vendor;
802 pplat->device = device;
803 pplat->class = class;
Simon Glassff3e0772015-03-05 12:25:25 -0700804 }
805
806 return 0;
807error:
808 printf("Cannot read bus configuration: %d\n", ret);
809
810 return ret;
811}
812
Simon Glassbf501592017-05-18 20:09:51 -0600813static int decode_regions(struct pci_controller *hose, ofnode parent_node,
814 ofnode node)
Simon Glassff3e0772015-03-05 12:25:25 -0700815{
816 int pci_addr_cells, addr_cells, size_cells;
817 int cells_per_record;
818 const u32 *prop;
819 int len;
820 int i;
821
Masahiro Yamada61e51ba2017-06-22 16:54:05 +0900822 prop = ofnode_get_property(node, "ranges", &len);
Simon Glassff3e0772015-03-05 12:25:25 -0700823 if (!prop)
824 return -EINVAL;
Simon Glass878d68c2017-06-12 06:21:31 -0600825 pci_addr_cells = ofnode_read_simple_addr_cells(node);
826 addr_cells = ofnode_read_simple_addr_cells(parent_node);
827 size_cells = ofnode_read_simple_size_cells(node);
Simon Glassff3e0772015-03-05 12:25:25 -0700828
829 /* PCI addresses are always 3-cells */
830 len /= sizeof(u32);
831 cells_per_record = pci_addr_cells + addr_cells + size_cells;
832 hose->region_count = 0;
833 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
834 cells_per_record);
835 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
836 u64 pci_addr, addr, size;
837 int space_code;
838 u32 flags;
839 int type;
Simon Glass9526d832015-11-19 20:26:58 -0700840 int pos;
Simon Glassff3e0772015-03-05 12:25:25 -0700841
842 if (len < cells_per_record)
843 break;
844 flags = fdt32_to_cpu(prop[0]);
845 space_code = (flags >> 24) & 3;
846 pci_addr = fdtdec_get_number(prop + 1, 2);
847 prop += pci_addr_cells;
848 addr = fdtdec_get_number(prop, addr_cells);
849 prop += addr_cells;
850 size = fdtdec_get_number(prop, size_cells);
851 prop += size_cells;
852 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
853 ", size=%" PRIx64 ", space_code=%d\n", __func__,
854 hose->region_count, pci_addr, addr, size, space_code);
855 if (space_code & 2) {
856 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
857 PCI_REGION_MEM;
858 } else if (space_code & 1) {
859 type = PCI_REGION_IO;
860 } else {
861 continue;
862 }
Tuomas Tynkkynen52ba9072018-05-14 18:47:50 +0300863
864 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
865 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
866 debug(" - beyond the 32-bit boundary, ignoring\n");
867 continue;
868 }
869
Simon Glass9526d832015-11-19 20:26:58 -0700870 pos = -1;
871 for (i = 0; i < hose->region_count; i++) {
872 if (hose->regions[i].flags == type)
873 pos = i;
874 }
875 if (pos == -1)
876 pos = hose->region_count++;
877 debug(" - type=%d, pos=%d\n", type, pos);
878 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
Simon Glassff3e0772015-03-05 12:25:25 -0700879 }
880
881 /* Add a region for our local memory */
Bernhard Messerklinger664758c2018-02-15 08:59:53 +0100882#ifdef CONFIG_NR_DRAM_BANKS
883 bd_t *bd = gd->bd;
884
Bin Meng1eaf7802018-03-27 00:46:05 -0700885 if (!bd)
886 return 0;
887
Bernhard Messerklinger664758c2018-02-15 08:59:53 +0100888 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
889 if (bd->bi_dram[i].size) {
890 pci_set_region(hose->regions + hose->region_count++,
891 bd->bi_dram[i].start,
892 bd->bi_dram[i].start,
893 bd->bi_dram[i].size,
894 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
895 }
896 }
897#else
898 phys_addr_t base = 0, size;
899
Simon Glass2084c5a2015-11-19 20:26:57 -0700900 size = gd->ram_size;
901#ifdef CONFIG_SYS_SDRAM_BASE
902 base = CONFIG_SYS_SDRAM_BASE;
903#endif
904 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
905 size = gd->pci_ram_top - base;
Bin Mengee1109b2018-03-27 00:46:06 -0700906 if (size)
907 pci_set_region(hose->regions + hose->region_count++, base,
908 base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
Bernhard Messerklinger664758c2018-02-15 08:59:53 +0100909#endif
Simon Glassff3e0772015-03-05 12:25:25 -0700910
911 return 0;
912}
913
914static int pci_uclass_pre_probe(struct udevice *bus)
915{
916 struct pci_controller *hose;
917 int ret;
918
919 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
920 bus->parent->name);
921 hose = bus->uclass_priv;
922
923 /* For bridges, use the top-level PCI controller */
Paul Burton65f62b12016-09-08 07:47:32 +0100924 if (!device_is_on_pci_bus(bus)) {
Simon Glassff3e0772015-03-05 12:25:25 -0700925 hose->ctlr = bus;
Simon Glassbf501592017-05-18 20:09:51 -0600926 ret = decode_regions(hose, dev_ofnode(bus->parent),
927 dev_ofnode(bus));
Simon Glassff3e0772015-03-05 12:25:25 -0700928 if (ret) {
929 debug("%s: Cannot decode regions\n", __func__);
930 return ret;
931 }
932 } else {
933 struct pci_controller *parent_hose;
934
935 parent_hose = dev_get_uclass_priv(bus->parent);
936 hose->ctlr = parent_hose->bus;
937 }
938 hose->bus = bus;
939 hose->first_busno = bus->seq;
940 hose->last_busno = bus->seq;
941
942 return 0;
943}
944
945static int pci_uclass_post_probe(struct udevice *bus)
946{
947 int ret;
948
Simon Glassff3e0772015-03-05 12:25:25 -0700949 debug("%s: probing bus %d\n", __func__, bus->seq);
950 ret = pci_bind_bus_devices(bus);
951 if (ret)
952 return ret;
953
954#ifdef CONFIG_PCI_PNP
955 ret = pci_auto_config_devices(bus);
Simon Glass4d214552015-09-08 17:52:47 -0600956 if (ret < 0)
957 return ret;
Simon Glassff3e0772015-03-05 12:25:25 -0700958#endif
959
Bin Meng348b7442015-08-20 06:40:23 -0700960#if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
961 /*
962 * Per Intel FSP specification, we should call FSP notify API to
963 * inform FSP that PCI enumeration has been done so that FSP will
964 * do any necessary initialization as required by the chipset's
965 * BIOS Writer's Guide (BWG).
966 *
967 * Unfortunately we have to put this call here as with driver model,
968 * the enumeration is all done on a lazy basis as needed, so until
969 * something is touched on PCI it won't happen.
970 *
971 * Note we only call this 1) after U-Boot is relocated, and 2)
972 * root bus has finished probing.
973 */
Simon Glass4d214552015-09-08 17:52:47 -0600974 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
Bin Meng348b7442015-08-20 06:40:23 -0700975 ret = fsp_init_phase_pci();
Simon Glass4d214552015-09-08 17:52:47 -0600976 if (ret)
977 return ret;
978 }
Bin Meng348b7442015-08-20 06:40:23 -0700979#endif
980
Simon Glass4d214552015-09-08 17:52:47 -0600981 return 0;
Simon Glassff3e0772015-03-05 12:25:25 -0700982}
983
984static int pci_uclass_child_post_bind(struct udevice *dev)
985{
986 struct pci_child_platdata *pplat;
987 struct fdt_pci_addr addr;
988 int ret;
989
Simon Glassbf501592017-05-18 20:09:51 -0600990 if (!dev_of_valid(dev))
Simon Glassff3e0772015-03-05 12:25:25 -0700991 return 0;
992
993 /*
994 * We could read vendor, device, class if available. But for now we
995 * just check the address.
996 */
997 pplat = dev_get_parent_platdata(dev);
Simon Glassbf501592017-05-18 20:09:51 -0600998 ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG, "reg",
999 &addr);
Simon Glassff3e0772015-03-05 12:25:25 -07001000
1001 if (ret) {
1002 if (ret != -ENOENT)
1003 return -EINVAL;
1004 } else {
Bin Mengdce54dd2015-08-20 06:40:26 -07001005 /* extract the devfn from fdt_pci_addr */
1006 pplat->devfn = addr.phys_hi & 0xff00;
Simon Glassff3e0772015-03-05 12:25:25 -07001007 }
1008
1009 return 0;
1010}
1011
Bin Meng4d8615c2015-07-19 00:20:04 +08001012static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
1013 uint offset, ulong *valuep,
1014 enum pci_size_t size)
Simon Glassff3e0772015-03-05 12:25:25 -07001015{
1016 struct pci_controller *hose = bus->uclass_priv;
Simon Glassff3e0772015-03-05 12:25:25 -07001017
1018 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1019}
1020
Bin Meng4d8615c2015-07-19 00:20:04 +08001021static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1022 uint offset, ulong value,
1023 enum pci_size_t size)
Simon Glassff3e0772015-03-05 12:25:25 -07001024{
1025 struct pci_controller *hose = bus->uclass_priv;
Simon Glassff3e0772015-03-05 12:25:25 -07001026
1027 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1028}
1029
Simon Glass76c3fbc2015-08-10 07:05:04 -06001030static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1031{
1032 struct udevice *dev;
1033 int ret = 0;
1034
1035 /*
1036 * Scan through all the PCI controllers. On x86 there will only be one
1037 * but that is not necessarily true on other hardware.
1038 */
1039 do {
1040 device_find_first_child(bus, &dev);
1041 if (dev) {
1042 *devp = dev;
1043 return 0;
1044 }
1045 ret = uclass_next_device(&bus);
1046 if (ret)
1047 return ret;
1048 } while (bus);
1049
1050 return 0;
1051}
1052
1053int pci_find_next_device(struct udevice **devp)
1054{
1055 struct udevice *child = *devp;
1056 struct udevice *bus = child->parent;
1057 int ret;
1058
1059 /* First try all the siblings */
1060 *devp = NULL;
1061 while (child) {
1062 device_find_next_child(&child);
1063 if (child) {
1064 *devp = child;
1065 return 0;
1066 }
1067 }
1068
1069 /* We ran out of siblings. Try the next bus */
1070 ret = uclass_next_device(&bus);
1071 if (ret)
1072 return ret;
1073
1074 return bus ? skip_to_next_device(bus, devp) : 0;
1075}
1076
1077int pci_find_first_device(struct udevice **devp)
1078{
1079 struct udevice *bus;
1080 int ret;
1081
1082 *devp = NULL;
1083 ret = uclass_first_device(UCLASS_PCI, &bus);
1084 if (ret)
1085 return ret;
1086
1087 return skip_to_next_device(bus, devp);
1088}
1089
Simon Glass9289db62015-11-19 20:26:59 -07001090ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1091{
1092 switch (size) {
1093 case PCI_SIZE_8:
1094 return (value >> ((offset & 3) * 8)) & 0xff;
1095 case PCI_SIZE_16:
1096 return (value >> ((offset & 2) * 8)) & 0xffff;
1097 default:
1098 return value;
1099 }
1100}
1101
1102ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1103 enum pci_size_t size)
1104{
1105 uint off_mask;
1106 uint val_mask, shift;
1107 ulong ldata, mask;
1108
1109 switch (size) {
1110 case PCI_SIZE_8:
1111 off_mask = 3;
1112 val_mask = 0xff;
1113 break;
1114 case PCI_SIZE_16:
1115 off_mask = 2;
1116 val_mask = 0xffff;
1117 break;
1118 default:
1119 return value;
1120 }
1121 shift = (offset & off_mask) * 8;
1122 ldata = (value & val_mask) << shift;
1123 mask = val_mask << shift;
1124 value = (old & ~mask) | ldata;
1125
1126 return value;
1127}
1128
Simon Glassf9260332015-11-19 20:27:01 -07001129int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1130 struct pci_region **memp, struct pci_region **prefp)
1131{
1132 struct udevice *bus = pci_get_controller(dev);
1133 struct pci_controller *hose = dev_get_uclass_priv(bus);
1134 int i;
1135
1136 *iop = NULL;
1137 *memp = NULL;
1138 *prefp = NULL;
1139 for (i = 0; i < hose->region_count; i++) {
1140 switch (hose->regions[i].flags) {
1141 case PCI_REGION_IO:
1142 if (!*iop || (*iop)->size < hose->regions[i].size)
1143 *iop = hose->regions + i;
1144 break;
1145 case PCI_REGION_MEM:
1146 if (!*memp || (*memp)->size < hose->regions[i].size)
1147 *memp = hose->regions + i;
1148 break;
1149 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1150 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1151 *prefp = hose->regions + i;
1152 break;
1153 }
1154 }
1155
1156 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1157}
1158
Simon Glassbab17cf2015-11-29 13:17:53 -07001159u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
1160{
1161 u32 addr;
1162 int bar;
1163
1164 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1165 dm_pci_read_config32(dev, bar, &addr);
1166 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1167 return addr & PCI_BASE_ADDRESS_IO_MASK;
1168 else
1169 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1170}
1171
Simon Glass9d731c82016-01-18 20:19:15 -07001172void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1173{
1174 int bar;
1175
1176 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1177 dm_pci_write_config32(dev, bar, addr);
1178}
1179
Simon Glass21d1fe72015-11-29 13:18:03 -07001180static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1181 pci_addr_t bus_addr, unsigned long flags,
1182 unsigned long skip_mask, phys_addr_t *pa)
1183{
1184 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1185 struct pci_region *res;
1186 int i;
1187
1188 for (i = 0; i < hose->region_count; i++) {
1189 res = &hose->regions[i];
1190
1191 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1192 continue;
1193
1194 if (res->flags & skip_mask)
1195 continue;
1196
1197 if (bus_addr >= res->bus_start &&
1198 (bus_addr - res->bus_start) < res->size) {
1199 *pa = (bus_addr - res->bus_start + res->phys_start);
1200 return 0;
1201 }
1202 }
1203
1204 return 1;
1205}
1206
1207phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1208 unsigned long flags)
1209{
1210 phys_addr_t phys_addr = 0;
1211 struct udevice *ctlr;
1212 int ret;
1213
1214 /* The root controller has the region information */
1215 ctlr = pci_get_controller(dev);
1216
1217 /*
1218 * if PCI_REGION_MEM is set we do a two pass search with preference
1219 * on matches that don't have PCI_REGION_SYS_MEMORY set
1220 */
1221 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1222 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1223 flags, PCI_REGION_SYS_MEMORY,
1224 &phys_addr);
1225 if (!ret)
1226 return phys_addr;
1227 }
1228
1229 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1230
1231 if (ret)
1232 puts("pci_hose_bus_to_phys: invalid physical address\n");
1233
1234 return phys_addr;
1235}
1236
1237int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1238 unsigned long flags, unsigned long skip_mask,
1239 pci_addr_t *ba)
1240{
1241 struct pci_region *res;
1242 struct udevice *ctlr;
1243 pci_addr_t bus_addr;
1244 int i;
1245 struct pci_controller *hose;
1246
1247 /* The root controller has the region information */
1248 ctlr = pci_get_controller(dev);
1249 hose = dev_get_uclass_priv(ctlr);
1250
1251 for (i = 0; i < hose->region_count; i++) {
1252 res = &hose->regions[i];
1253
1254 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1255 continue;
1256
1257 if (res->flags & skip_mask)
1258 continue;
1259
1260 bus_addr = phys_addr - res->phys_start + res->bus_start;
1261
1262 if (bus_addr >= res->bus_start &&
1263 (bus_addr - res->bus_start) < res->size) {
1264 *ba = bus_addr;
1265 return 0;
1266 }
1267 }
1268
1269 return 1;
1270}
1271
1272pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1273 unsigned long flags)
1274{
1275 pci_addr_t bus_addr = 0;
1276 int ret;
1277
1278 /*
1279 * if PCI_REGION_MEM is set we do a two pass search with preference
1280 * on matches that don't have PCI_REGION_SYS_MEMORY set
1281 */
1282 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1283 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1284 PCI_REGION_SYS_MEMORY, &bus_addr);
1285 if (!ret)
1286 return bus_addr;
1287 }
1288
1289 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1290
1291 if (ret)
1292 puts("pci_hose_phys_to_bus: invalid physical address\n");
1293
1294 return bus_addr;
1295}
1296
1297void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1298{
1299 pci_addr_t pci_bus_addr;
1300 u32 bar_response;
1301
1302 /* read BAR address */
1303 dm_pci_read_config32(dev, bar, &bar_response);
1304 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1305
1306 /*
1307 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1308 * isn't actualy used on any platform because u-boot assumes a static
1309 * linear mapping. In the future, this could read the BAR size
1310 * and pass that as the size if needed.
1311 */
1312 return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1313}
1314
Simon Glassff3e0772015-03-05 12:25:25 -07001315UCLASS_DRIVER(pci) = {
1316 .id = UCLASS_PCI,
1317 .name = "pci",
Simon Glass2bb02e42015-05-10 21:08:06 -06001318 .flags = DM_UC_FLAG_SEQ_ALIAS,
Simon Glass91195482016-07-05 17:10:10 -06001319 .post_bind = dm_scan_fdt_dev,
Simon Glassff3e0772015-03-05 12:25:25 -07001320 .pre_probe = pci_uclass_pre_probe,
1321 .post_probe = pci_uclass_post_probe,
1322 .child_post_bind = pci_uclass_child_post_bind,
1323 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1324 .per_child_platdata_auto_alloc_size =
1325 sizeof(struct pci_child_platdata),
1326};
1327
1328static const struct dm_pci_ops pci_bridge_ops = {
1329 .read_config = pci_bridge_read_config,
1330 .write_config = pci_bridge_write_config,
1331};
1332
1333static const struct udevice_id pci_bridge_ids[] = {
1334 { .compatible = "pci-bridge" },
1335 { }
1336};
1337
1338U_BOOT_DRIVER(pci_bridge_drv) = {
1339 .name = "pci_bridge_drv",
1340 .id = UCLASS_PCI,
1341 .of_match = pci_bridge_ids,
1342 .ops = &pci_bridge_ops,
1343};
1344
1345UCLASS_DRIVER(pci_generic) = {
1346 .id = UCLASS_PCI_GENERIC,
1347 .name = "pci_generic",
1348};
1349
1350static const struct udevice_id pci_generic_ids[] = {
1351 { .compatible = "pci-generic" },
1352 { }
1353};
1354
1355U_BOOT_DRIVER(pci_generic_drv) = {
1356 .name = "pci_generic_drv",
1357 .id = UCLASS_PCI_GENERIC,
1358 .of_match = pci_generic_ids,
1359};
Stephen Warrene578b922016-01-26 11:10:11 -07001360
1361void pci_init(void)
1362{
1363 struct udevice *bus;
1364
1365 /*
1366 * Enumerate all known controller devices. Enumeration has the side-
1367 * effect of probing them, so PCIe devices will be enumerated too.
1368 */
1369 for (uclass_first_device(UCLASS_PCI, &bus);
1370 bus;
1371 uclass_next_device(&bus)) {
1372 ;
1373 }
1374}