TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 1 | /* |
| 2 | * MCF5329 Internal Memory Map |
| 3 | * |
| 4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
| 5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 6 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __IMMAP_5235__ |
| 11 | #define __IMMAP_5235__ |
| 12 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 13 | #define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000) |
| 14 | #define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040) |
| 15 | #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080) |
| 16 | #define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100) |
| 17 | #define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110) |
| 18 | #define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120) |
| 19 | #define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130) |
| 20 | #define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200) |
| 21 | #define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240) |
| 22 | #define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280) |
| 23 | #define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300) |
| 24 | #define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340) |
| 25 | #define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400) |
| 26 | #define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440) |
| 27 | #define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480) |
| 28 | #define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0) |
| 29 | #define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00) |
| 30 | #define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00) |
| 31 | #define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00) |
| 32 | #define MMAP_FEC (CONFIG_SYS_MBAR + 0x00001000) |
| 33 | #define MMAP_FECFIFO (CONFIG_SYS_MBAR + 0x00001400) |
| 34 | #define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000) |
| 35 | #define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110000) |
| 36 | #define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000) |
| 37 | #define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000) |
| 38 | #define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000) |
| 39 | #define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000) |
| 40 | #define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000) |
| 41 | #define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000) |
| 42 | #define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000) |
| 43 | #define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000) |
| 44 | #define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000) |
| 45 | #define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000) |
| 46 | #define MMAP_CAN1 (CONFIG_SYS_MBAR + 0x001C0000) |
| 47 | #define MMAP_ETPU (CONFIG_SYS_MBAR + 0x001D0000) |
| 48 | #define MMAP_CAN2 (CONFIG_SYS_MBAR + 0x001F0000) |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 49 | |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 50 | #include <asm/coldfire/eport.h> |
| 51 | #include <asm/coldfire/flexbus.h> |
| 52 | #include <asm/coldfire/flexcan.h> |
| 53 | #include <asm/coldfire/intctrl.h> |
| 54 | #include <asm/coldfire/mdha.h> |
| 55 | #include <asm/coldfire/qspi.h> |
| 56 | #include <asm/coldfire/rng.h> |
| 57 | #include <asm/coldfire/skha.h> |
| 58 | |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 59 | /* System Control Module register */ |
| 60 | typedef struct scm_ctrl { |
| 61 | u32 ipsbar; /* 0x00 - MBAR */ |
| 62 | u32 res1; /* 0x04 */ |
| 63 | u32 rambar; /* 0x08 - RAMBAR */ |
| 64 | u32 res2; /* 0x0C */ |
| 65 | u8 crsr; /* 0x10 Core Reset Status Register */ |
| 66 | u8 cwcr; /* 0x11 Core Watchdog Control Register */ |
| 67 | u8 lpicr; /* 0x12 Low-Power Interrupt Control Register */ |
| 68 | u8 cwsr; /* 0x13 Core Watchdog Service Register */ |
| 69 | u32 dmareqc; /* 0x14 */ |
| 70 | u32 res3; /* 0x18 */ |
| 71 | u32 mpark; /* 0x1C */ |
| 72 | u8 mpr; /* 0x20 */ |
| 73 | u8 res4[3]; /* 0x21 - 0x23 */ |
| 74 | u8 pacr0; /* 0x24 */ |
| 75 | u8 pacr1; /* 0x25 */ |
| 76 | u8 pacr2; /* 0x26 */ |
| 77 | u8 pacr3; /* 0x27 */ |
| 78 | u8 pacr4; /* 0x28 */ |
| 79 | u32 res5; /* 0x29 */ |
| 80 | u8 pacr5; /* 0x2a */ |
| 81 | u8 pacr6; /* 0x2b */ |
| 82 | u8 pacr7; /* 0x2c */ |
| 83 | u32 res6; /* 0x2d */ |
| 84 | u8 pacr8; /* 0x2e */ |
| 85 | u32 res7; /* 0x2f */ |
| 86 | u8 gpacr; /* 0x30 */ |
| 87 | u8 res8[3]; /* 0x31 - 0x33 */ |
| 88 | } scm_t; |
| 89 | |
| 90 | /* SDRAM controller registers */ |
| 91 | typedef struct sdram_ctrl { |
| 92 | u16 dcr; /* 0x00 Control register */ |
| 93 | u16 res1[3]; /* 0x02 - 0x07 */ |
| 94 | u32 dacr0; /* 0x08 address and control register 0 */ |
| 95 | u32 dmr0; /* 0x0C mask register block 0 */ |
| 96 | u32 dacr1; /* 0x10 address and control register 1 */ |
| 97 | u32 dmr1; /* 0x14 mask register block 1 */ |
| 98 | } sdram_t; |
| 99 | |
TsiChung Liew | 012522f | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 100 | typedef struct canex_ctrl { |
| 101 | can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */ |
| 102 | } canex_t; |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 103 | |
| 104 | /* GPIO port registers */ |
| 105 | typedef struct gpio_ctrl { |
| 106 | /* Port Output Data Registers */ |
| 107 | u8 podr_addr; /* 0x00 */ |
| 108 | u8 podr_datah; /* 0x01 */ |
| 109 | u8 podr_datal; /* 0x02 */ |
| 110 | u8 podr_busctl; /* 0x03 */ |
| 111 | u8 podr_bs; /* 0x04 */ |
| 112 | u8 podr_cs; /* 0x05 */ |
| 113 | u8 podr_sdram; /* 0x06 */ |
| 114 | u8 podr_feci2c; /* 0x07 */ |
| 115 | u8 podr_uarth; /* 0x08 */ |
| 116 | u8 podr_uartl; /* 0x09 */ |
| 117 | u8 podr_qspi; /* 0x0A */ |
| 118 | u8 podr_timer; /* 0x0B */ |
| 119 | u8 podr_etpu; /* 0x0C */ |
| 120 | u8 res1[3]; /* 0x0D - 0x0F */ |
| 121 | |
| 122 | /* Port Data Direction Registers */ |
| 123 | u8 pddr_addr; /* 0x10 */ |
| 124 | u8 pddr_datah; /* 0x11 */ |
| 125 | u8 pddr_datal; /* 0x12 */ |
| 126 | u8 pddr_busctl; /* 0x13 */ |
| 127 | u8 pddr_bs; /* 0x14 */ |
| 128 | u8 pddr_cs; /* 0x15 */ |
| 129 | u8 pddr_sdram; /* 0x16 */ |
| 130 | u8 pddr_feci2c; /* 0x17 */ |
| 131 | u8 pddr_uarth; /* 0x18 */ |
| 132 | u8 pddr_uartl; /* 0x19 */ |
| 133 | u8 pddr_qspi; /* 0x1A */ |
| 134 | u8 pddr_timer; /* 0x1B */ |
| 135 | u8 pddr_etpu; /* 0x1C */ |
| 136 | u8 res2[3]; /* 0x1D - 0x1F */ |
| 137 | |
| 138 | /* Port Data Direction Registers */ |
| 139 | u8 ppdsdr_addr; /* 0x20 */ |
| 140 | u8 ppdsdr_datah; /* 0x21 */ |
| 141 | u8 ppdsdr_datal; /* 0x22 */ |
| 142 | u8 ppdsdr_busctl; /* 0x23 */ |
| 143 | u8 ppdsdr_bs; /* 0x24 */ |
| 144 | u8 ppdsdr_cs; /* 0x25 */ |
| 145 | u8 ppdsdr_sdram; /* 0x26 */ |
| 146 | u8 ppdsdr_feci2c; /* 0x27 */ |
| 147 | u8 ppdsdr_uarth; /* 0x28 */ |
| 148 | u8 ppdsdr_uartl; /* 0x29 */ |
| 149 | u8 ppdsdr_qspi; /* 0x2A */ |
| 150 | u8 ppdsdr_timer; /* 0x2B */ |
| 151 | u8 ppdsdr_etpu; /* 0x2C */ |
| 152 | u8 res3[3]; /* 0x2D - 0x2F */ |
| 153 | |
| 154 | /* Port Clear Output Data Registers */ |
| 155 | u8 pclrr_addr; /* 0x30 */ |
| 156 | u8 pclrr_datah; /* 0x31 */ |
| 157 | u8 pclrr_datal; /* 0x32 */ |
| 158 | u8 pclrr_busctl; /* 0x33 */ |
| 159 | u8 pclrr_bs; /* 0x34 */ |
| 160 | u8 pclrr_cs; /* 0x35 */ |
| 161 | u8 pclrr_sdram; /* 0x36 */ |
| 162 | u8 pclrr_feci2c; /* 0x37 */ |
| 163 | u8 pclrr_uarth; /* 0x38 */ |
| 164 | u8 pclrr_uartl; /* 0x39 */ |
| 165 | u8 pclrr_qspi; /* 0x3A */ |
| 166 | u8 pclrr_timer; /* 0x3B */ |
| 167 | u8 pclrr_etpu; /* 0x3C */ |
| 168 | u8 res4[3]; /* 0x3D - 0x3F */ |
| 169 | |
| 170 | /* Pin Assignment Registers */ |
| 171 | u8 par_ad; /* 0x40 */ |
| 172 | u8 res5; /* 0x41 */ |
| 173 | u16 par_busctl; /* 0x42 */ |
| 174 | u8 par_bs; /* 0x44 */ |
| 175 | u8 par_cs; /* 0x45 */ |
| 176 | u8 par_sdram; /* 0x46 */ |
| 177 | u8 par_feci2c; /* 0x47 */ |
| 178 | u16 par_uart; /* 0x48 */ |
| 179 | u8 par_qspi; /* 0x4A */ |
| 180 | u8 res6; /* 0x4B */ |
| 181 | u16 par_timer; /* 0x4C */ |
| 182 | u8 par_etpu; /* 0x4E */ |
| 183 | u8 res7; /* 0x4F */ |
| 184 | |
| 185 | /* Drive Strength Control Registers */ |
| 186 | u8 dscr_eim; /* 0x50 */ |
| 187 | u8 dscr_etpu; /* 0x51 */ |
| 188 | u8 dscr_feci2c; /* 0x52 */ |
| 189 | u8 dscr_uart; /* 0x53 */ |
| 190 | u8 dscr_qspi; /* 0x54 */ |
| 191 | u8 dscr_timer; /* 0x55 */ |
| 192 | u16 res8; /* 0x56 */ |
| 193 | } gpio_t; |
| 194 | |
| 195 | /*Chip configuration module registers */ |
| 196 | typedef struct ccm_ctrl { |
| 197 | u8 rcr; /* 0x01 */ |
| 198 | u8 rsr; /* 0x02 */ |
| 199 | u16 res1; /* 0x03 */ |
| 200 | u16 ccr; /* 0x04 Chip configuration register */ |
| 201 | u16 lpcr; /* 0x06 Low-power Control register */ |
| 202 | u16 rcon; /* 0x08 Rreset configuration register */ |
| 203 | u16 cir; /* 0x0a Chip identification register */ |
| 204 | } ccm_t; |
| 205 | |
| 206 | /* Clock Module registers */ |
| 207 | typedef struct pll_ctrl { |
| 208 | u32 syncr; /* 0x00 synthesizer control register */ |
| 209 | u32 synsr; /* 0x04 synthesizer status register */ |
| 210 | } pll_t; |
| 211 | |
| 212 | /* Watchdog registers */ |
| 213 | typedef struct wdog_ctrl { |
| 214 | u16 cr; /* 0x00 Control register */ |
| 215 | u16 mr; /* 0x02 Modulus register */ |
| 216 | u16 cntr; /* 0x04 Count register */ |
| 217 | u16 sr; /* 0x06 Service register */ |
| 218 | } wdog_t; |
| 219 | |
TsiChungLiew | 4a442d3 | 2007-08-16 19:23:50 -0500 | [diff] [blame] | 220 | #endif /* __IMMAP_5235__ */ |