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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Sergey Temerkhanov746f9852015-10-14 09:55:50 -07002/**
3 * (C) Copyright 2014, Cavium Inc.
Sergey Temerkhanov746f9852015-10-14 09:55:50 -07004**/
5
6#ifndef __THUNDERX_88XX_H__
7#define __THUNDERX_88XX_H__
8
9#define CONFIG_REMAKE_ELF
10
11#define CONFIG_THUNDERX
12
13#define CONFIG_SYS_64BIT
14
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070015#define MEM_BASE 0x00500000
16
Sergey Temerkhanov900f88f2015-10-14 09:55:51 -070017#define CONFIG_SYS_LOWMEM_BASE MEM_BASE
18
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070019/* Link Definitions */
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070020#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
21
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070022/* SMP Spin Table Definitions */
23#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
24
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070025/* Generic Timer Definitions */
26#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
27
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070028#define CONFIG_SYS_MEMTEST_START MEM_BASE
29#define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE)
30
31/* Size of malloc() pool */
32#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
33
34/* PL011 Serial Configuration */
35
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070036#define CONFIG_PL011_CLOCK 24000000
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070037
38/* Generic Interrupt Controller Definitions */
39#define GICD_BASE (0x801000000000)
40#define GICR_BASE (0x801000002000)
41#define CONFIG_SYS_SERIAL0 0x87e024000000
42#define CONFIG_SYS_SERIAL1 0x87e025000000
43
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070044/* BOOTP options */
45#define CONFIG_BOOTP_BOOTFILESIZE
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070046
47/* Miscellaneous configurable options */
48#define CONFIG_SYS_LOAD_ADDR (MEM_BASE)
49
50/* Physical Memory Map */
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070051#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */
52#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */
53#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
54
55/* Initial environment variables */
56#define UBOOT_IMG_HEAD_SIZE 0x40
57/* C80000 - 0x40 */
58#define CONFIG_EXTRA_ENV_SETTINGS \
59 "kernel_addr=08007ffc0\0" \
60 "fdt_addr=0x94C00000\0" \
61 "fdt_high=0x9fffffff\0"
62
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070063/* Do not preserve environment */
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070064#define CONFIG_ENV_SIZE 0x1000
65
66/* Monitor Command Prompt */
67#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070068#define CONFIG_SYS_MAXARGS 64 /* max command args */
69#define CONFIG_NO_RELOCATION 1
Sergey Temerkhanov746f9852015-10-14 09:55:50 -070070#define PLL_REF_CLK 50000000 /* 50 MHz */
71#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK)
72
73#endif /* __THUNDERX_88XX_H__ */