wdenk | 7abf0c5 | 2004-04-18 21:45:42 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003 Embedded Edge, LLC |
| 3 | * Dan Malek <dan@embeddededge.com> |
| 4 | * Copied from ADS85xx. |
| 5 | * Updates for Silicon Tx GP3 8560 board. |
| 6 | * |
| 7 | * (C) Copyright 2002,2003 Motorola,Inc. |
| 8 | * Xianghua Xiao <X.Xiao@motorola.com> |
| 9 | * |
| 10 | * See file CREDITS for list of people who contributed to this |
| 11 | * project. |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or |
| 14 | * modify it under the terms of the GNU General Public License as |
| 15 | * published by the Free Software Foundation; either version 2 of |
| 16 | * the License, or (at your option) any later version. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License |
| 24 | * along with this program; if not, write to the Free Software |
| 25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 26 | * MA 02111-1307 USA |
| 27 | */ |
| 28 | |
| 29 | /* mpc8560ads board configuration file */ |
| 30 | /* please refer to doc/README.mpc85xx for more info */ |
| 31 | /* make sure you change the MAC address and other network params first, |
| 32 | * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file |
| 33 | */ |
| 34 | |
| 35 | #ifndef __CONFIG_H |
| 36 | #define __CONFIG_H |
| 37 | |
| 38 | /* High Level Configuration Options */ |
| 39 | #define CONFIG_BOOKE 1 /* BOOKE */ |
| 40 | #define CONFIG_E500 1 /* BOOKE e500 family */ |
| 41 | #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ |
| 42 | #define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */ |
| 43 | #define CONFIG_MPC8560 1 /* MPC8560 specific */ |
| 44 | #define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/ |
| 45 | |
| 46 | #undef CONFIG_PCI /* pci ethernet support */ |
| 47 | #define CONFIG_TSEC_ENET /* tsec ethernet support*/ |
| 48 | #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ |
| 49 | #define CONFIG_ENV_OVERWRITE |
| 50 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ |
| 51 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
| 52 | |
| 53 | #if defined(CONFIG_MPC85xx_REV1) |
| 54 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ |
| 55 | #endif |
| 56 | |
| 57 | /* Using Localbus SDRAM to emulate flash before we can program the flash, |
| 58 | * normally you need a flash-boot image(u-boot.bin), if so undef this. |
| 59 | */ |
| 60 | #undef CONFIG_RAM_AS_FLASH |
| 61 | |
| 62 | #define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */ |
| 63 | |
| 64 | /* Blinkin' LEDs for Robert :-) |
| 65 | */ |
| 66 | #define CONFIG_SHOW_ACTIVITY 1 |
| 67 | |
| 68 | #if !defined(CONFIG_SPD_EEPROM) /* manually set up DDR parameters */ |
| 69 | #define CONFIG_DDR_SETTING |
| 70 | #endif |
| 71 | |
| 72 | /* below can be toggled for performance analysis. otherwise use default */ |
| 73 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| 74 | #undef CONFIG_BTB /* toggle branch predition */ |
| 75 | #undef CONFIG_ADDR_STREAMING /* toggle addr streaming */ |
| 76 | |
| 77 | #define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ |
| 78 | |
| 79 | #undef CFG_DRAM_TEST /* memory test, takes time */ |
| 80 | #define CFG_MEMTEST_START 0x00200000 /* memtest region */ |
| 81 | #define CFG_MEMTEST_END 0x00400000 |
| 82 | |
| 83 | #if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \ |
| 84 | defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \ |
| 85 | defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC)) |
| 86 | #error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC." |
| 87 | #endif |
| 88 | |
| 89 | /* |
| 90 | * Base addresses -- Note these are effective addresses where the |
| 91 | * actual resources get mapped (not physical addresses) |
| 92 | */ |
| 93 | #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ |
| 94 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE |
| 95 | |
| 96 | /* GPPP supports up to 2G of DRAM. Allocate up to 1G until we get |
| 97 | * a chance to try it out. Actual size is always read from sdram eeprom. |
| 98 | */ |
| 99 | #define CFG_SDRAM_SIZE 1024 /* DDR is 1GB */ |
| 100 | |
| 101 | /* Localbus SDRAM is an option, not all boards have it. |
| 102 | */ |
| 103 | #if defined(CONFIG_RAM_AS_FLASH) |
| 104 | #define CFG_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ |
| 105 | #else |
| 106 | #define CFG_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */ |
| 107 | #endif |
| 108 | #define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ |
| 109 | |
| 110 | #if defined(CONFIG_RAM_AS_FLASH) |
| 111 | #define CFG_FLASH_BASE 0xf8000000 /* start of FLASH 16M */ |
| 112 | #define CFG_BR0_PRELIM 0xf8001801 /* port size 32bit */ |
| 113 | #else /* Boot from real Flash */ |
| 114 | #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
| 115 | #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ |
| 116 | #endif |
| 117 | |
| 118 | #define CFG_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */ |
| 119 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ |
| 120 | #define CFG_MAX_FLASH_SECT 136 /* sectors per device */ |
| 121 | #undef CFG_FLASH_CHECKSUM |
| 122 | #define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */ |
| 123 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
| 124 | |
| 125 | /* The configuration latch is Chip Select 1. |
| 126 | * It's an 8-bit latch in the upper 8 bits of the word. |
| 127 | */ |
| 128 | #define CFG_BR1_PRELIM 0xfc001801 /* 32-bit port */ |
| 129 | #define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */ |
| 130 | #define CFG_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */ |
| 131 | |
| 132 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
| 133 | |
| 134 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
| 135 | #define CFG_RAMBOOT |
| 136 | #else |
| 137 | #undef CFG_RAMBOOT |
| 138 | #endif |
| 139 | |
| 140 | #ifdef CFG_RAMBOOT |
| 141 | #define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ |
| 142 | #else |
| 143 | #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
| 144 | #endif |
| 145 | #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ |
| 146 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
| 147 | |
| 148 | |
| 149 | #define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */ |
| 150 | |
| 151 | #if defined(CONFIG_DDR_SETTING) |
| 152 | #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ |
| 153 | #define CFG_DDR_CS0_CONFIG 0x80000002 |
| 154 | #define CFG_DDR_TIMING_1 0x37344321 |
| 155 | #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning*/ |
| 156 | #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR*/ |
| 157 | #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ |
| 158 | #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page*/ |
| 159 | #endif |
| 160 | |
| 161 | #undef CONFIG_CLOCKS_IN_MHZ |
| 162 | |
| 163 | /* local bus definitions */ |
| 164 | #define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ |
| 165 | #define CFG_OR2_PRELIM 0xfc006901 |
| 166 | #define CFG_LBC_LCRR 0x00030004 /* local bus freq */ |
| 167 | #define CFG_LBC_LBCR 0x00000000 |
| 168 | #define CFG_LBC_LSRT 0x20000000 |
| 169 | #define CFG_LBC_MRTPR 0x20000000 |
| 170 | #define CFG_LBC_LSDMR_1 0x2861b723 |
| 171 | #define CFG_LBC_LSDMR_2 0x0861b723 |
| 172 | #define CFG_LBC_LSDMR_3 0x0861b723 |
| 173 | #define CFG_LBC_LSDMR_4 0x1861b723 |
| 174 | #define CFG_LBC_LSDMR_5 0x4061b723 |
| 175 | |
| 176 | #define CONFIG_L1_INIT_RAM |
| 177 | #define CFG_INIT_RAM_LOCK 1 |
| 178 | #define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ |
| 179 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
| 180 | |
| 181 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
| 182 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 183 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
| 184 | |
| 185 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 186 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
| 187 | |
| 188 | /* Serial Port */ |
| 189 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ |
| 190 | #undef CONFIG_CONS_NONE /* define if console on something else */ |
| 191 | #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ |
| 192 | |
| 193 | #define CONFIG_BAUDRATE 38400 |
| 194 | |
| 195 | #define CFG_BAUDRATE_TABLE \ |
| 196 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
| 197 | |
| 198 | /* Use the HUSH parser */ |
| 199 | #define CFG_HUSH_PARSER |
| 200 | #ifdef CFG_HUSH_PARSER |
| 201 | #define CFG_PROMPT_HUSH_PS2 "> " |
| 202 | #endif |
| 203 | |
| 204 | /* I2C */ |
| 205 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ |
| 206 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
| 207 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 208 | #define CFG_I2C_SLAVE 0x7F |
| 209 | #if 0 |
| 210 | #define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */ |
| 211 | #else |
| 212 | /* I did the 'if 0' so we could keep the syntax above if ever needed. */ |
| 213 | #undef CFG_I2C_NOPROBES |
| 214 | #endif |
| 215 | |
| 216 | #define CFG_PCI_MEM_BASE 0xe0000000 |
| 217 | #define CFG_PCI_MEM_PHYS 0xe0000000 |
| 218 | #define CFG_PCI_MEM_SIZE 0x10000000 |
| 219 | |
| 220 | #if defined(CONFIG_PCI) /* PCI Ethernet card */ |
| 221 | #define CONFIG_NET_MULTI |
| 222 | #define CONFIG_EEPRO100 |
| 223 | #undef CONFIG_TULIP |
| 224 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 225 | #if !defined(CONFIG_PCI_PNP) |
| 226 | #define PCI_ENET0_IOADDR 0xe0000000 |
| 227 | #define PCI_ENET0_MEMADDR 0xe0000000 |
| 228 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
| 229 | #endif |
| 230 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ |
| 231 | #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
| 232 | #if defined(CONFIG_MPC85xx_REV1) /* Errata PCI 7 */ |
| 233 | #define CFG_PCI_SUBSYS_DEVICEID 0x0003 |
| 234 | #else |
| 235 | #define CFG_PCI_SUBSYS_DEVICEID 0x0009 |
| 236 | #endif |
| 237 | #elif defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */ |
| 238 | #define CONFIG_NET_MULTI 1 |
| 239 | #define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */ |
| 240 | #define CONFIG_MII 1 /* MII PHY management */ |
| 241 | #define CONFIG_PHY_ADDR 8 /* PHY address */ |
| 242 | #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ |
| 243 | #define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */ |
| 244 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ |
| 245 | #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ |
| 246 | #if (CONFIG_ETHER_INDEX == 2) |
| 247 | /* |
| 248 | * - Rx-CLK is CLK13 |
| 249 | * - Tx-CLK is CLK14 |
| 250 | * - Select bus for bd/buffers |
| 251 | * - Full duplex |
| 252 | */ |
| 253 | #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
| 254 | #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) |
| 255 | #define CFG_CPMFCR_RAMTYPE 0 |
| 256 | #if 0 |
| 257 | #define CFG_FCC_PSMR (FCC_PSMR_FDE) |
| 258 | #else |
| 259 | #define CFG_FCC_PSMR 0 |
| 260 | #endif |
| 261 | #define FETH2_RST 0x01 |
| 262 | #elif (CONFIG_ETHER_INDEX == 3) |
| 263 | /* need more definitions here for FE3 */ |
| 264 | #define FETH3_RST 0x80 |
| 265 | #endif /* CONFIG_ETHER_INDEX */ |
| 266 | #define CONFIG_MII /* MII PHY management */ |
| 267 | #undef CONFIG_BITBANGMII /* bit-bang MII PHY management */ |
| 268 | /* |
| 269 | * GPIO pins used for bit-banged MII communications |
| 270 | */ |
| 271 | #define MDIO_PORT 2 /* Port C */ |
| 272 | #define MDIO_ACTIVE (iop->pdir |= 0x00400000) |
| 273 | #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) |
| 274 | #define MDIO_READ ((iop->pdat & 0x00400000) != 0) |
| 275 | |
| 276 | #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ |
| 277 | else iop->pdat &= ~0x00400000 |
| 278 | |
| 279 | #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ |
| 280 | else iop->pdat &= ~0x00200000 |
| 281 | |
| 282 | #define MIIDELAY udelay(1) |
| 283 | #endif |
| 284 | |
| 285 | /* Environment */ |
| 286 | /* We use the top boot sector flash, so we have some 16K sectors for env |
| 287 | * But....functions don't seem smart enough yet. |
| 288 | */ |
| 289 | #ifndef CFG_RAMBOOT |
| 290 | #if defined(CONFIG_RAM_AS_FLASH) |
| 291 | #define CFG_ENV_IS_NOWHERE |
| 292 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) |
| 293 | #define CFG_ENV_SIZE 0x2000 |
| 294 | #else |
| 295 | #define CFG_ENV_IS_IN_FLASH 1 |
| 296 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x60000) |
| 297 | #define CFG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */ |
| 298 | #endif |
| 299 | #define CFG_ENV_SIZE 0x2000 |
| 300 | #else |
| 301 | #define CFG_NO_FLASH 1 /* Flash is not usable now */ |
| 302 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
| 303 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
| 304 | #define CFG_ENV_SIZE 0x2000 |
| 305 | #endif |
| 306 | |
| 307 | #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400" |
| 308 | #define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xff900000" |
| 309 | #define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ |
| 310 | |
| 311 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 312 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 313 | |
| 314 | #if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) |
| 315 | #if defined(CONFIG_PCI) |
| 316 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ |
| 317 | CFG_CMD_PING | CFG_CMD_I2C) & \ |
| 318 | ~(CFG_CMD_ENV | \ |
| 319 | CFG_CMD_LOADS )) |
| 320 | #elif defined(CONFIG_TSEC_ENET) |
| 321 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \ |
| 322 | CFG_CMD_MII | CFG_CMD_I2C ) & \ |
| 323 | ~(CFG_CMD_ENV)) |
| 324 | #elif defined(CONFIG_ETHER_ON_FCC) |
| 325 | #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ |
| 326 | CFG_CMD_PING | CFG_CMD_I2C) & \ |
| 327 | ~(CFG_CMD_ENV)) |
| 328 | #endif |
| 329 | #else |
| 330 | #if defined(CONFIG_PCI) |
| 331 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ |
| 332 | CFG_CMD_PING | CFG_CMD_I2C) |
| 333 | #elif defined(CONFIG_TSEC_ENET) |
| 334 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \ |
| 335 | CFG_CMD_MII | CFG_CMD_I2C) |
| 336 | #elif defined(CONFIG_ETHER_ON_FCC) |
| 337 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ |
| 338 | CFG_CMD_PING | CFG_CMD_I2C) |
| 339 | #endif |
| 340 | #endif |
| 341 | #include <cmd_confdefs.h> |
| 342 | |
| 343 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 344 | |
| 345 | /* |
| 346 | * Miscellaneous configurable options |
| 347 | */ |
| 348 | #define CFG_LONGHELP /* undef to save memory */ |
| 349 | #define CFG_PROMPT "GPPP=> " /* Monitor Command Prompt */ |
| 350 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 351 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 352 | #else |
| 353 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
| 354 | #endif |
| 355 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 356 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 357 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 358 | #define CFG_LOAD_ADDR 0x1000000 /* default load address */ |
| 359 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| 360 | |
| 361 | /* |
| 362 | * For booting Linux, the board info and command line data |
| 363 | * have to be in the first 8 MB of memory, since this is |
| 364 | * the maximum mapped by the Linux kernel during initialization. |
| 365 | */ |
| 366 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 367 | |
| 368 | /* Cache Configuration */ |
| 369 | #define CFG_DCACHE_SIZE 32768 |
| 370 | #define CFG_CACHELINE_SIZE 32 |
| 371 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 372 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| 373 | #endif |
| 374 | |
| 375 | /* |
| 376 | * Internal Definitions |
| 377 | * |
| 378 | * Boot Flags |
| 379 | */ |
| 380 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 381 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 382 | |
| 383 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 384 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 385 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ |
| 386 | #endif |
| 387 | |
| 388 | /*Note: change below for your network setting!!! */ |
| 389 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) |
| 390 | #define CONFIG_ETHADDR 00:01:af:07:9b:8a |
| 391 | #define CONFIG_ETH1ADDR 00:01:af:07:9b:8b |
| 392 | #define CONFIG_ETH2ADDR 00:01:af:07:9b:8c |
| 393 | #endif |
| 394 | |
| 395 | #define CONFIG_SERVERIP 192.168.85.1 |
| 396 | #define CONFIG_IPADDR 192.168.85.60 |
| 397 | #define CONFIG_GATEWAYIP 192.168.85.1 |
| 398 | #define CONFIG_NETMASK 255.255.255.0 |
| 399 | #define CONFIG_HOSTNAME STX_GP3 |
| 400 | #define CONFIG_ROOTPATH /gppproot |
| 401 | #define CONFIG_BOOTFILE uImage |
| 402 | |
| 403 | #endif /* __CONFIG_H */ |