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wdenka56bd922004-06-06 23:13:55 +00001/*
wdenk1eaeb582004-06-08 00:22:43 +00002 * (C) Copyright 2003-2004
wdenka56bd922004-06-06 23:13:55 +00003 * MPC Data Limited (http://www.mpc-data.co.uk)
4 * Dave Peverley <dpeverley at mpc-data.co.uk>
5 *
6 * Configuation settings for the TI OMAP Perseus 2 board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenk1eaeb582004-06-08 00:22:43 +000018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenka56bd922004-06-06 23:13:55 +000019 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
wdenka56bd922004-06-06 23:13:55 +000030/*
31 * If we are developing, we might want to start armboot from ram
32 * so we MUST NOT initialize critical regs like mem-timing ...
33 */
34
wdenk1eaeb582004-06-08 00:22:43 +000035#define CONFIG_INIT_CRITICAL /* undef for developing */
wdenka56bd922004-06-06 23:13:55 +000036
37/* allow to overwrite serial and ethaddr */
38#define CONFIG_ENV_OVERWRITE
39
wdenka56bd922004-06-06 23:13:55 +000040/*
41 * High Level Configuration Options
42 * (easy to change)
43 */
44
wdenk1eaeb582004-06-08 00:22:43 +000045#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
46#define CONFIG_OMAP 1 /* in a TI OMAP core */
47#define CONFIG_OMAP730 1 /* which is in a 730 */
48#define CONFIG_P2_OMAP730 1 /* a Perseus 2 Board */
wdenka56bd922004-06-06 23:13:55 +000049
wdenk1eaeb582004-06-08 00:22:43 +000050/*
51 * Input clock of PLL
52 * The OMAP730 Perseus 2 has 13MHz input clock
wdenka56bd922004-06-06 23:13:55 +000053 */
54
wdenk1eaeb582004-06-08 00:22:43 +000055#define CONFIG_SYS_CLK_FREQ 13000000
wdenka56bd922004-06-06 23:13:55 +000056
wdenk1eaeb582004-06-08 00:22:43 +000057#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
wdenka56bd922004-06-06 23:13:55 +000058
59#define CONFIG_MISC_INIT_R
60
wdenk1eaeb582004-06-08 00:22:43 +000061#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
wdenka56bd922004-06-06 23:13:55 +000062#define CONFIG_SETUP_MEMORY_TAGS 1
63
wdenka56bd922004-06-06 23:13:55 +000064/*
65 * Size of malloc() pool
66 */
67
wdenk1eaeb582004-06-08 00:22:43 +000068#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
69#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenka56bd922004-06-06 23:13:55 +000070
71/*
72 * Hardware drivers
73 */
74
75#define CONFIG_DRIVER_LAN91C96
wdenk1eaeb582004-06-08 00:22:43 +000076#define CONFIG_LAN91C96_BASE 0x04000300
wdenka56bd922004-06-06 23:13:55 +000077#define CONFIG_LAN91C96_EXT_PHY
78
wdenka56bd922004-06-06 23:13:55 +000079/*
80 * NS16550 Configuration
81 */
82
83#define CFG_NS16550
84#define CFG_NS16550_SERIAL
wdenk1eaeb582004-06-08 00:22:43 +000085#define CFG_NS16550_REG_SIZE (1)
86#define CFG_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
87#define CFG_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
88 * on perseus */
wdenka56bd922004-06-06 23:13:55 +000089
90/*
91 * select serial console configuration
92 */
93
wdenk1eaeb582004-06-08 00:22:43 +000094#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP730 Perseus 2 */
wdenka56bd922004-06-06 23:13:55 +000095
wdenk1eaeb582004-06-08 00:22:43 +000096#define CONFIG_CONS_INDEX 1
97#define CONFIG_BAUDRATE 115200
98#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenka56bd922004-06-06 23:13:55 +000099
wdenk1eaeb582004-06-08 00:22:43 +0000100#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP)
101#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
wdenka56bd922004-06-06 23:13:55 +0000102
wdenk1eaeb582004-06-08 00:22:43 +0000103/*
104 * This must be included AFTER the definition of CONFIG_COMMANDS (if any)
wdenka56bd922004-06-06 23:13:55 +0000105 */
106
107#include <cmd_confdefs.h>
108#include <configs/omap730.h>
109#include <configs/h2_p2_dbg_board.h>
110
wdenk1eaeb582004-06-08 00:22:43 +0000111#define CONFIG_BOOTDELAY 3
112#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
wdenka56bd922004-06-06 23:13:55 +0000113
wdenk1eaeb582004-06-08 00:22:43 +0000114#define CONFIG_LOADADDR 0x10000000
wdenka56bd922004-06-06 23:13:55 +0000115
116#define CONFIG_ETHADDR
wdenk1eaeb582004-06-08 00:22:43 +0000117#define CONFIG_NETMASK 255.255.255.0
118#define CONFIG_IPADDR 192.168.0.23
119#define CONFIG_SERVERIP 192.150.0.100
120#define CONFIG_BOOTFILE "uImage" /* File to load */
wdenka56bd922004-06-06 23:13:55 +0000121
122#if defined (CONFIG_COMMANDS) && defined (CFG_CMD_KGDB)
wdenk1eaeb582004-06-08 00:22:43 +0000123#define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */
124#define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */
wdenka56bd922004-06-06 23:13:55 +0000125#endif
126
wdenka56bd922004-06-06 23:13:55 +0000127/*
128 * Miscellaneous configurable options
129 */
130
wdenk1eaeb582004-06-08 00:22:43 +0000131#define CFG_LONGHELP /* undef to save memory */
132#define CFG_PROMPT "OMAP730 P2 # " /* Monitor Command Prompt */
133#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenka56bd922004-06-06 23:13:55 +0000134/* Print Buffer Size */
wdenk1eaeb582004-06-08 00:22:43 +0000135#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
136#define CFG_MAXARGS 16 /* max number of command args */
137#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
wdenka56bd922004-06-06 23:13:55 +0000138
wdenk1eaeb582004-06-08 00:22:43 +0000139#define CFG_MEMTEST_START 0x10000000 /* memtest works on */
140#define CFG_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
wdenka56bd922004-06-06 23:13:55 +0000141
wdenk1eaeb582004-06-08 00:22:43 +0000142#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
wdenka56bd922004-06-06 23:13:55 +0000143
wdenk1eaeb582004-06-08 00:22:43 +0000144#define CFG_LOAD_ADDR 0x10000000 /* default load address */
wdenka56bd922004-06-06 23:13:55 +0000145
wdenk1eaeb582004-06-08 00:22:43 +0000146/* The OMAP730 has 3 general purpose MPU timers, they can be driven by
147 * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
wdenka56bd922004-06-06 23:13:55 +0000148 * local divisor.
149 */
150
wdenk1eaeb582004-06-08 00:22:43 +0000151#define CFG_TIMERBASE 0xFFFEC500 /* use timer 1 */
152#define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */
153#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
wdenka56bd922004-06-06 23:13:55 +0000154
155/*-----------------------------------------------------------------------
156 * Stack sizes
157 *
158 * The stack sizes are set up in start.S using the settings below
159 */
160
wdenk1eaeb582004-06-08 00:22:43 +0000161#define CONFIG_STACKSIZE (128*1024) /* regular stack */
wdenka56bd922004-06-06 23:13:55 +0000162#ifdef CONFIG_USE_IRQ
wdenk1eaeb582004-06-08 00:22:43 +0000163#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
164#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
wdenka56bd922004-06-06 23:13:55 +0000165#endif
166
wdenka56bd922004-06-06 23:13:55 +0000167/*-----------------------------------------------------------------------
168 * Physical Memory Map
169 */
170
wdenk1eaeb582004-06-08 00:22:43 +0000171#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
172#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
173#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
wdenka56bd922004-06-06 23:13:55 +0000174
175#if defined(CONFIG_CS0_BOOT)
wdenk1eaeb582004-06-08 00:22:43 +0000176#define PHYS_FLASH_1 0x0C000000
wdenka56bd922004-06-06 23:13:55 +0000177#elif defined(CONFIG_CS3_BOOT)
wdenk1eaeb582004-06-08 00:22:43 +0000178#define PHYS_FLASH_1 0x00000000
wdenka56bd922004-06-06 23:13:55 +0000179#else
180#error Unknown Boot Chip-Select number
181#endif
182
wdenk1eaeb582004-06-08 00:22:43 +0000183#define CFG_FLASH_BASE PHYS_FLASH_1
wdenka56bd922004-06-06 23:13:55 +0000184
185/*-----------------------------------------------------------------------
186 * FLASH and environment organization
187 */
188
wdenk1eaeb582004-06-08 00:22:43 +0000189#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
190#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
191#define CFG_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
wdenka56bd922004-06-06 23:13:55 +0000192/* addr of environment */
wdenk1eaeb582004-06-08 00:22:43 +0000193#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x020000)
wdenka56bd922004-06-06 23:13:55 +0000194
195/* timeout values are in ticks */
wdenk1eaeb582004-06-08 00:22:43 +0000196#define CFG_FLASH_ERASE_TOUT (20*CFG_HZ) /* Timeout for Flash Erase */
197#define CFG_FLASH_WRITE_TOUT (20*CFG_HZ) /* Timeout for Flash Write */
wdenka56bd922004-06-06 23:13:55 +0000198
wdenk1eaeb582004-06-08 00:22:43 +0000199#define CFG_ENV_IS_IN_FLASH 1
200#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
201#define CFG_ENV_OFFSET 0x20000 /* environment starts here */
wdenka56bd922004-06-06 23:13:55 +0000202
wdenk1eaeb582004-06-08 00:22:43 +0000203#endif /* ! __CONFIG_H */