blob: f44bb2aa25d4865157e9eb12edc67523003ce9af [file] [log] [blame]
York Suna4c66502012-08-17 08:22:39 +00001Table of interleaving 2-4 controllers
2=====================================
3 +--------------+-----------------------------------------------------------+
4 |Configuration | Memory Controller |
5 | | 1 2 3 4 |
6 |--------------+--------------+--------------+-----------------------------+
7 | Two memory | Not Intlv'ed | Not Intlv'ed | |
8 | complexes +--------------+--------------+ |
9 | | 2-way Intlv'ed | |
10 |--------------+--------------+--------------+--------------+ |
11 | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | |
12 | Three memory +--------------+--------------+--------------+ |
13 | complexes | 2-way Intlv'ed | Not Intlv'ed | |
14 | +-----------------------------+--------------+ |
15 | | 3-way Intlv'ed | |
16 +--------------+--------------+--------------+--------------+--------------+
17 | | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed | Not Intlv'ed |
18 | Four memory +--------------+--------------+--------------+--------------+
19 | complexes | 2-way Intlv'ed | 2-way Intlv'ed |
20 | +-----------------------------+-----------------------------+
21 | | 4-way Intlv'ed |
22 +--------------+-----------------------------------------------------------+
Haiying Wangc9ffd832008-10-03 12:37:10 -040023
York Suna4c66502012-08-17 08:22:39 +000024
25Table of 2-way interleaving modes supported in cpu/8xxx/ddr/
Haiying Wangc9ffd832008-10-03 12:37:10 -040026======================================================
27 +-------------+---------------------------------------------------------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +010028 | | Rank Interleaving |
29 | +--------+-----------+-----------+------------+-----------+
30 |Memory | | | | 2x2 | 4x1 |
31 |Controller | None | 2x1 lower | 2x1 upper | {CS0+CS1}, | {CS0+CS1+ |
32 |Interleaving | | {CS0+CS1} | {CS2+CS3} | {CS2+CS3} | CS2+CS3} |
Haiying Wangc9ffd832008-10-03 12:37:10 -040033 +-------------+--------+-----------+-----------+------------+-----------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +010034 |None | Yes | Yes | Yes | Yes | Yes |
Haiying Wangc9ffd832008-10-03 12:37:10 -040035 +-------------+--------+-----------+-----------+------------+-----------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +010036 |Cacheline | Yes | Yes | No | No, Only(*)| Yes |
37 | |CS0 Only| | | {CS0+CS1} | |
Haiying Wangc9ffd832008-10-03 12:37:10 -040038 +-------------+--------+-----------+-----------+------------+-----------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +010039 |Page | Yes | Yes | No | No, Only(*)| Yes |
40 | |CS0 Only| | | {CS0+CS1} | |
Haiying Wangc9ffd832008-10-03 12:37:10 -040041 +-------------+--------+-----------+-----------+------------+-----------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +010042 |Bank | Yes | Yes | No | No, Only(*)| Yes |
43 | |CS0 Only| | | {CS0+CS1} | |
Haiying Wangc9ffd832008-10-03 12:37:10 -040044 +-------------+--------+-----------+-----------+------------+-----------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +010045 |Superbank | No | Yes | No | No, Only(*)| Yes |
46 | | | | | {CS0+CS1} | |
Haiying Wangc9ffd832008-10-03 12:37:10 -040047 +-------------+--------+-----------+-----------+------------+-----------+
48 (*) Although the hardware can be configured with memory controller
49 interleaving using "2x2" rank interleaving, it only interleaves {CS0+CS1}
50 from each controller. {CS2+CS3} on each controller are only rank
51 interleaved on that controller.
52
york076bff82010-07-02 22:25:52 +000053 For memory controller interleaving, identical DIMMs are suggested. Software
54 doesn't check the size or organization of interleaved DIMMs.
55
Haiying Wangc9ffd832008-10-03 12:37:10 -040056The ways to configure the ddr interleaving mode
57==============================================
581. In board header file(e.g.MPC8572DS.h), add default interleaving setting
Tom Rini0613c362022-12-04 10:03:50 -050059 under "CFG_EXTRA_ENV_SETTINGS", like:
60 #define CFG_EXTRA_ENV_SETTINGS \
Kumar Gala79e4e642010-07-14 10:04:21 -050061 "hwconfig=fsl_ddr:ctlr_intlv=bank" \
Haiying Wangc9ffd832008-10-03 12:37:10 -040062 ......
63
Bin Menga1875592016-02-05 19:30:11 -0800642. Run U-Boot "setenv" command to configure the memory interleaving mode.
Haiying Wangc9ffd832008-10-03 12:37:10 -040065 Either numerical or string value is accepted.
66
67 # disable memory controller interleaving
Kumar Gala79e4e642010-07-14 10:04:21 -050068 setenv hwconfig "fsl_ddr:ctlr_intlv=null"
Haiying Wangc9ffd832008-10-03 12:37:10 -040069
70 # cacheline interleaving
Kumar Gala79e4e642010-07-14 10:04:21 -050071 setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
Haiying Wangc9ffd832008-10-03 12:37:10 -040072
73 # page interleaving
Kumar Gala79e4e642010-07-14 10:04:21 -050074 setenv hwconfig "fsl_ddr:ctlr_intlv=page"
Haiying Wangc9ffd832008-10-03 12:37:10 -040075
76 # bank interleaving
Kumar Gala79e4e642010-07-14 10:04:21 -050077 setenv hwconfig "fsl_ddr:ctlr_intlv=bank"
Haiying Wangc9ffd832008-10-03 12:37:10 -040078
79 # superbank
Kumar Gala79e4e642010-07-14 10:04:21 -050080 setenv hwconfig "fsl_ddr:ctlr_intlv=superbank"
Haiying Wangc9ffd832008-10-03 12:37:10 -040081
York Suna4c66502012-08-17 08:22:39 +000082 # 1KB 3-way interleaving
83 setenv hwconfig "fsl_ddr:ctlr_intlv=3way_1KB"
84
85 # 4KB 3-way interleaving
86 setenv hwconfig "fsl_ddr:ctlr_intlv=3way_4KB"
87
88 # 8KB 3-way interleaving
89 setenv hwconfig "fsl_ddr:ctlr_intlv=3way_8KB"
90
Haiying Wangc9ffd832008-10-03 12:37:10 -040091 # disable bank (chip-select) interleaving
Kumar Gala79e4e642010-07-14 10:04:21 -050092 setenv hwconfig "fsl_ddr:bank_intlv=null"
Haiying Wangc9ffd832008-10-03 12:37:10 -040093
94 # bank(chip-select) interleaving cs0+cs1
Kumar Gala79e4e642010-07-14 10:04:21 -050095 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1"
Haiying Wangc9ffd832008-10-03 12:37:10 -040096
97 # bank(chip-select) interleaving cs2+cs3
Kumar Gala79e4e642010-07-14 10:04:21 -050098 setenv hwconfig "fsl_ddr:bank_intlv=cs2_cs3"
Haiying Wangc9ffd832008-10-03 12:37:10 -040099
100 # bank(chip-select) interleaving (cs0+cs1) and (cs2+cs3) (2x2)
Kumar Gala79e4e642010-07-14 10:04:21 -0500101 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_and_cs2_cs3"
Haiying Wangc9ffd832008-10-03 12:37:10 -0400102
103 # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
Kumar Gala79e4e642010-07-14 10:04:21 -0500104 setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
105
York Sun89b78092012-10-08 07:44:27 +0000106 # bank(chip-select) interleaving (auto)
107 setenv hwconfig "fsl_ddr:bank_intlv=auto"
108 This auto mode only select from cs0_cs1_cs2_cs3, cs0_cs1, null dependings
109 on DIMMs.
110
york7fd101c2010-07-02 22:25:54 +0000111Memory controller address hashing
112==================================
113If the DDR controller supports address hashing, it can be enabled by hwconfig.
114
115Syntax is:
116hwconfig=fsl_ddr:addr_hash=true
117
York Sun47df8f02011-01-10 12:02:57 +0000118Memory controller ECC on/off
119============================
120If ECC is enabled in board configuratoin file, i.e. #define CONFIG_DDR_ECC,
121ECC can be turned on/off by hwconfig.
122
123Syntax is
124hwconfig=fsl_ddr:ecc=off
York Sunebbe11d2010-09-28 15:20:33 -0700125
Shengzhou Liueb118802016-03-10 17:36:56 +0800126
127Memory address parity on/off
128============================
129address parity can be turned on/off by hwconfig.
130Syntax is:
131hwconfig=fsl_ddr:parity=on
132
133
York Sunebbe11d2010-09-28 15:20:33 -0700134Memory testing options for mpc85xx
135==================================
Bin Menga1875592016-02-05 19:30:11 -08001361. Memory test can be done once U-Boot prompt comes up using mtest, or
York Sunebbe11d2010-09-28 15:20:33 -07001372. Memory test can be done with Power-On-Self-Test function, activated at
138 compile time.
139
Tom Rini9cebc4a2022-11-19 18:45:44 -0500140 In order to enable the POST memory test, CFG_POST needs to be
York Sunebbe11d2010-09-28 15:20:33 -0700141 defined in board configuraiton header file. By default, POST memory test
142 performs a fast test. A slow test can be enabled by changing the flag at
143 compiling time. To test memory bigger than 2GB, 36BIT support is needed.
144 Memory is tested within a 2GB window. TLBs are used to map the virtual 2GB
145 window to physical address so that all physical memory can be tested.
146
york7fd101c2010-07-02 22:25:54 +0000147Combination of hwconfig
148=======================
149Hwconfig can be combined with multiple parameters, for example, on a supported
150platform
151
York Sune1fd16b2011-01-10 12:03:00 +0000152hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
153
Shengzhou Liueb118802016-03-10 17:36:56 +0800154
York Sune1fd16b2011-01-10 12:03:00 +0000155Table for dynamic ODT for DDR3
156==============================
157For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may
158be needed, depending on the configuration. The numbers in the following tables are
159in Ohms.
160
161* denotes dynamic ODT
162
163Two slots system
164+-----------------------+----------+---------------+-----------------------------+-----------------------------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100165| Configuration | |DRAM controller| Slot 1 | Slot 2 |
York Sune1fd16b2011-01-10 12:03:00 +0000166+-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100167| | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 |
168+ Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+
169| | | | | | Write | Read | Write | Read | Write | Read | Write | Read |
York Sune1fd16b2011-01-10 12:03:00 +0000170+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100171| | | Slot 1 | off | 75 | 120 | off | off | off | off | off | 30 | 30 |
York Sune1fd16b2011-01-10 12:03:00 +0000172| Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100173| | | Slot 2 | off | 75 | off | off | 30 | 30 | 120 | off | off | off |
York Sune1fd16b2011-01-10 12:03:00 +0000174+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100175| | | Slot 1 | off | 75 | 120 | off | off | off | 20 | 20 | | |
York Sune1fd16b2011-01-10 12:03:00 +0000176| Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100177| | | Slot 2 | off | 75 | off | off | 20 | 20 | 120 *| off | | |
York Sune1fd16b2011-01-10 12:03:00 +0000178+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100179| | | Slot 1 | off | 75 | 120 *| off | | | off | off | 20 | 20 |
York Sune1fd16b2011-01-10 12:03:00 +0000180|Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100181| | | Slot 2 | off | 75 | 20 | 20 | | | 120 | off | off | off |
York Sune1fd16b2011-01-10 12:03:00 +0000182+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100183| | | Slot 1 | off | 75 | 120 *| off | | | 30 | 30 | | |
York Sune1fd16b2011-01-10 12:03:00 +0000184|Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100185| | | Slot 2 | off | 75 | 30 | 30 | | | 120 *| off | | |
York Sune1fd16b2011-01-10 12:03:00 +0000186+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100187| Dual Rank | Empty | Slot 1 | off | 75 | 40 | off | off | off | | | | |
York Sune1fd16b2011-01-10 12:03:00 +0000188+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100189| Empty | Dual Rank | Slot 2 | off | 75 | | | | | 40 | off | off | off |
York Sune1fd16b2011-01-10 12:03:00 +0000190+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100191|Single Rank| Empty | Slot 1 | off | 75 | 40 | off | | | | | | |
York Sune1fd16b2011-01-10 12:03:00 +0000192+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100193| Empty |Single Rank| Slot 2 | off | 75 | | | | | 40 | off | | |
York Sune1fd16b2011-01-10 12:03:00 +0000194+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
195
196Single slot system
197+-------------+------------+---------------+-----------------------------+-----------------------------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100198| | |DRAM controller| Rank 1 | Rank 2 | Rank 3 | Rank 4 |
York Sune1fd16b2011-01-10 12:03:00 +0000199|Configuration| Write/Read |-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100200| | | Write | Read | Write | Read | Write | Read | Write | Read | Write | Read |
York Sune1fd16b2011-01-10 12:03:00 +0000201+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100202| | R1 | off | 75 | 120 *| off | off | off | 20 | 20 | off | off |
203| |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
204| | R2 | off | 75 | off | 20 | 120 | off | 20 | 20 | off | off |
York Sune1fd16b2011-01-10 12:03:00 +0000205| Quad Rank |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100206| | R3 | off | 75 | 20 | 20 | off | off | 120 *| off | off | off |
207| |------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
208| | R4 | off | 75 | 20 | 20 | off | off | off | 20 | 120 | off |
York Sune1fd16b2011-01-10 12:03:00 +0000209+-------------+------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100210| | R1 | off | 75 | 40 | off | off | off |
York Sune1fd16b2011-01-10 12:03:00 +0000211| Dual Rank |------------+-------+-------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100212| | R2 | off | 75 | 40 | off | off | off |
York Sune1fd16b2011-01-10 12:03:00 +0000213+-------------+------------+-------+-------+-------+------+-------+------+
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100214| Single Rank | R1 | off | 75 | 40 | off |
York Sune1fd16b2011-01-10 12:03:00 +0000215+-------------+------------+-------+-------+-------+------+
216
217Reference http://www.xrosstalkmag.com/mag_issues/xrosstalk_oct08_final.pdf
Wolfgang Denkd1a24f02011-02-02 22:36:10 +0100218 http://download.micron.com/pdf/technotes/ddr3/tn4108_ddr3_design_guide.pdf
York Sun4e573822011-08-26 11:32:43 -0700219
220
221Table for ODT for DDR2
222======================
223Two slots system
224+-----------------------+----------+---------------+-----------------------------+-----------------------------+
225| Configuration | |DRAM controller| Slot 1 | Slot 2 |
226+-----------+-----------+----------+-------+-------+--------------+--------------+--------------+--------------+
227| | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 |
228+ Slot 1 | Slot 2 |Write/Read| Write | Read |-------+------+-------+------+-------+------+-------+------+
229| | | | | | Write | Read | Write | Read | Write | Read | Write | Read |
230+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
231| | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | off | off |
232| Dual Rank | Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
233| | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | off | off |
234+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
235| | | Slot 1 | off | 150 | off | off | off | off | 75 | 75 | | |
236| Dual Rank |Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
237| | | Slot 2 | off | 150 | 75 | 75 | off | off | off | off | | |
238+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
239| | | Slot 1 | off | 150 | off | off | | | 75 | 75 | off | off |
240|Single Rank| Dual Rank |----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
241| | | Slot 2 | off | 150 | 75 | 75 | | | off | off | off | off |
242+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
243| | | Slot 1 | off | 150 | off | off | | | 75 | 75 | | |
244|Single Rank|Single Rank|----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
245| | | Slot 2 | off | 150 | 75 | 75 | | | off | off | | |
246+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
247| Dual Rank | Empty | Slot 1 | off | 75 | 150 | off | off | off | | | | |
248+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
249| Empty | Dual Rank | Slot 2 | off | 75 | | | | | 150 | off | off | off |
250+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
251|Single Rank| Empty | Slot 1 | off | 75 | 150 | off | | | | | | |
252+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
253| Empty |Single Rank| Slot 2 | off | 75 | | | | | 150 | off | | |
254+-----------+-----------+----------+-------+-------+-------+------+-------+------+-------+------+-------+------+
255
256Single slot system
257+-------------+------------+---------------+-----------------------------+
258| | |DRAM controller| Rank 1 | Rank 2 |
259|Configuration| Write/Read |-------+-------+-------+------+-------+------+
260| | | Write | Read | Write | Read | Write | Read |
261+-------------+------------+-------+-------+-------+------+-------+------+
262| | R1 | off | 75 | 150 | off | off | off |
263| Dual Rank |------------+-------+-------+-------+------+-------+------+
264| | R2 | off | 75 | 150 | off | off | off |
265+-------------+------------+-------+-------+-------+------+-------+------+
266| Single Rank | R1 | off | 75 | 150 | off |
267+-------------+------------+-------+-------+-------+------+
268
269Reference http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/ddr2_odt_control_200603.pdf
270
York Sun6f5e1dc2011-09-16 13:21:35 -0700271
272Interactive DDR debugging
273===========================
274
James Yang02a9ce72013-01-04 08:14:03 +0000275For DDR parameter tuning up and debugging, the interactive DDR debugger can
276be activated by setting the environment variable "ddr_interactive" to any
277value. (The value of ddr_interactive may have a meaning in the future, but,
278for now, the presence of the variable will cause the debugger to run.) Once
Bin Menga1875592016-02-05 19:30:11 -0800279activated, U-Boot will show the prompt "FSL DDR>" before enabling the DDR
James Yang02a9ce72013-01-04 08:14:03 +0000280controller. The available commands are printed by typing "help".
York Sun6f5e1dc2011-09-16 13:21:35 -0700281
James Yang02a9ce72013-01-04 08:14:03 +0000282Another way to enter the interactive DDR debugger without setting the
283environment variable is to send the 'd' character early during the boot
284process. To save booting time, no additional delay is added, so the window
285to send the key press is very short -- basically, it is the time before the
286memory controller code starts to run. For example, when rebooting from
Bin Menga1875592016-02-05 19:30:11 -0800287within U-Boot, the user must press 'd' IMMEDIATELY after hitting enter to
James Yang02a9ce72013-01-04 08:14:03 +0000288initiate a 'reset' command. In case of power on/reset, the user can hold
289down the 'd' key while applying power or hitting the board's reset button.
York Sune750cfa2013-01-04 08:13:59 +0000290
York Sun6f5e1dc2011-09-16 13:21:35 -0700291The example flow of using interactive debugging is
292type command "compute" to calculate the parameters from the default
293type command "print" with arguments to show SPD, options, registers
294type command "edit" with arguments to change any if desired
James Yang5926ee32013-01-04 08:14:02 +0000295type command "copy" with arguments to copy controller/dimm settings
York Sun6f5e1dc2011-09-16 13:21:35 -0700296type command "go" to continue calculation and enable DDR controller
James Yang02a9ce72013-01-04 08:14:03 +0000297
298Additional commands to restart the debugging are:
York Sun6f5e1dc2011-09-16 13:21:35 -0700299type command "reset" to reset the board
300type command "recompute" to reload SPD and start over
301
302Note, check "next_step" to show the flow. For example, after edit opts, the
303next_step is STEP_ASSIGN_ADDRESSES. After editing registers, the next_step is
James Yang02a9ce72013-01-04 08:14:03 +0000304STEP_PROGRAM_REGS. Upon issuing command "go", the debugger will program the
305DDR controller with the current setting without further calculation and then
306exit to resume the booting of the machine.
York Sun6f5e1dc2011-09-16 13:21:35 -0700307
308The detail syntax for each commands are
309
310print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
311 c<n> - the controller number, eg. c0, c1
312 d<n> - the DIMM number, eg. d0, d1
313 spd - print SPD data
Thomas Weberc46bf092012-03-24 22:44:01 +0000314 dimmparms - DIMM parameters, calculated from SPD
York Sun6f5e1dc2011-09-16 13:21:35 -0700315 commonparms - lowest common parameters for all DIMMs
316 opts - options
317 addresses - address assignment (not implemented yet)
318 regs - controller registers
319
320edit <c#> <d#> <spd|dimmparms|commonparms|opts|addresses|regs> <element> <value>
321 c<n> - the controller number, eg. c0, c1
322 d<n> - the DIMM number, eg. d0, d1
323 spd - print SPD data
Thomas Weberc46bf092012-03-24 22:44:01 +0000324 dimmparms - DIMM parameters, calculated from SPD
York Sun6f5e1dc2011-09-16 13:21:35 -0700325 commonparms - lowest common parameters for all DIMMs
326 opts - options
327 addresses - address assignment (not implemented yet)
328 regs - controller registers
329 <element> - name of the modified element
330 byte number if the object is SPD
331 <value> - decimal or heximal (prefixed with 0x) numbers
332
James Yang5926ee32013-01-04 08:14:02 +0000333copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>
334 same as for "edit" command
335 DIMM numbers ignored for commonparms, opts, and regs
336
York Sun6f5e1dc2011-09-16 13:21:35 -0700337reset
338 no arguement - reset the board
339
340recompute
341 no argument - reload SPD and start over
342
343compute
344 no argument - recompute from current next_step
345
346next_step
347 no argument - show current next_step
348
349help
350 no argument - print a list of all commands
351
352go
Bin Menga1875592016-02-05 19:30:11 -0800353 no argument - program memory controller(s) and continue with U-Boot
York Sun6f5e1dc2011-09-16 13:21:35 -0700354
355Examples of debugging flow
356
357 FSL DDR>compute
358 Detected UDIMM UG51U6400N8SU-ACF
James Yang02a9ce72013-01-04 08:14:03 +0000359 FSL DDR>print
York Sun6f5e1dc2011-09-16 13:21:35 -0700360 print [c<n>] [d<n>] [spd] [dimmparms] [commonparms] [opts] [addresses] [regs]
361 FSL DDR>print dimmparms
362 DIMM parameters: Controller=0 DIMM=0
363 DIMM organization parameters:
364 module part name = UG51U6400N8SU-ACF
365 rank_density = 2147483648 bytes (2048 megabytes)
366 capacity = 4294967296 bytes (4096 megabytes)
367 burst_lengths_bitmask = 0C
368 base_addresss = 0 (00000000 00000000)
369 n_ranks = 2
370 data_width = 64
371 primary_sdram_width = 64
372 ec_sdram_width = 0
373 registered_dimm = 0
374 n_row_addr = 15
375 n_col_addr = 10
376 edc_config = 0
377 n_banks_per_sdram_device = 8
378 tCKmin_X_ps = 1500
379 tCKmin_X_minus_1_ps = 0
380 tCKmin_X_minus_2_ps = 0
381 tCKmax_ps = 0
382 caslat_X = 960
383 tAA_ps = 13125
384 caslat_X_minus_1 = 0
385 caslat_X_minus_2 = 0
386 caslat_lowest_derated = 0
387 tRCD_ps = 13125
388 tRP_ps = 13125
389 tRAS_ps = 36000
390 tWR_ps = 15000
391 tWTR_ps = 7500
392 tRFC_ps = 160000
393 tRRD_ps = 6000
394 tRC_ps = 49125
395 refresh_rate_ps = 7800000
396 tIS_ps = 0
397 tIH_ps = 0
398 tDS_ps = 0
399 tDH_ps = 0
400 tRTP_ps = 7500
401 tDQSQ_max_ps = 0
402 tQHS_ps = 0
403 FSL DDR>edit c0 opts ECC_mode 0
404 FSL DDR>edit c0 regs cs0_bnds 0x000000FF
405 FSL DDR>go
406 2 GiB left unmapped
407 4 GiB (DDR3, 64-bit, CL=9, ECC off)
408 DDR Chip-Select Interleaving Mode: CS0+CS1
409 Testing 0x00000000 - 0x7fffffff
410 Testing 0x80000000 - 0xffffffff
411 Remap DDR 2 GiB left unmapped
412
413 POST memory PASSED
414 Flash: 128 MiB
415 L2: 128 KB enabled
416 Corenet Platform Cache: 1024 KB enabled
417 SERDES: timeout resetting bank 3
418 SRIO1: disabled
419 SRIO2: disabled
420 MMC: FSL_ESDHC: 0
421 EEPROM: Invalid ID (ff ff ff ff)
422 PCIe1: disabled
423 PCIe2: Root Complex, x1, regs @ 0xfe201000
424 01:00.0 - 8086:10d3 - Network controller
425 PCIe2: Bus 00 - 01
426 PCIe3: disabled
427 In: serial
428 Out: serial
429 Err: serial
430 Net: Initializing Fman
431 Fman1: Uploading microcode version 101.8.0
432 e1000: 00:1b:21:81:d2:e0
433 FM1@DTSEC1, FM1@DTSEC2, FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5, e1000#0 [PRIME]
434 Warning: e1000#0 MAC addresses don't match:
435 Address in SROM is 00:1b:21:81:d2:e0
436 Address in environment is 00:e0:0c:00:ea:05
437
438 Hit any key to stop autoboot: 0
439 =>