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Patrice Chotard01aabf92019-02-19 00:37:20 +01001// SPDX-License-Identifier: GPL-2.0+
2
3#include <stm32f7-u-boot.dtsi>
4/{
5 chosen {
6 bootargs = "root=/dev/mmcblk0p1 rw rootwait";
7 };
8
9 aliases {
10 /* Aliases for gpios so as to use sequence */
11 gpio0 = &gpioa;
12 gpio1 = &gpiob;
13 gpio2 = &gpioc;
14 gpio3 = &gpiod;
15 gpio4 = &gpioe;
16 gpio5 = &gpiof;
17 gpio6 = &gpiog;
18 gpio7 = &gpioh;
19 gpio8 = &gpioi;
20 gpio9 = &gpioj;
21 gpio10 = &gpiok;
Patrice Chotardfe63d3c2019-02-19 16:49:05 +010022 mmc0 = &sdio1;
Patrice Chotard01aabf92019-02-19 00:37:20 +010023 spi0 = &qspi;
24 };
25
26 button1 {
27 compatible = "st,button1";
28 button-gpio = <&gpioc 13 0>;
29 };
30
31 led1 {
32 compatible = "st,led1";
33 led-gpio = <&gpiof 10 0>;
34 };
35};
36
37&fmc {
38 /*
39 * Memory configuration from sdram datasheet IS42S32800G-6BLI
40 */
41 bank1: bank@0 {
42 u-boot,dm-pre-reloc;
43 st,sdram-control = /bits/ 8 <NO_COL_9
44 NO_ROW_12
45 MWIDTH_32
46 BANKS_4
47 CAS_2
48 SDCLK_3
49 RD_BURST_EN
50 RD_PIPE_DL_0>;
51 st,sdram-timing = /bits/ 8 <TMRD_1
52 TXSR_1
53 TRAS_1
54 TRC_6
55 TRP_2
56 TWR_1
57 TRCD_1>;
58 st,sdram-refcount = <1539>;
59 };
60};
61
62&mac {
63 phy-mode = "mii";
64};
65
66&pinctrl {
67 ethernet_mii: mii@0 {
68 pins {
Patrice Chotardfe63d3c2019-02-19 16:49:05 +010069 pinmux = <STM32_PINMUX('A', 0, AF11)>, /*ETH_MII_CRS */
70 <STM32_PINMUX('A', 1, AF11)>, /*ETH_MII_RX_CLK */
71 <STM32_PINMUX('A', 7, AF11)>, /*ETH_MII_RX_DV */
72 <STM32_PINMUX('A', 8, AF0)>, /*ETH_MII_MCO1 */
73 <STM32_PINMUX('G',13, AF11)>, /*ETH_MII_TXD0 */
74 <STM32_PINMUX('G',14, AF11)>, /*ETH_MII_TXD1 */
75 <STM32_PINMUX('C', 2, AF11)>, /*ETH_MII_TXD2 */
76 <STM32_PINMUX('E', 2, AF11)>, /*ETH_MII_TXD3 */
77 <STM32_PINMUX('C', 3, AF11)>, /*ETH_MII_TX_CLK */
78 <STM32_PINMUX('C', 4, AF11)>, /*ETH_MII_RXD0 */
79 <STM32_PINMUX('C', 5, AF11)>, /*ETH_MII_RXD1 */
80 <STM32_PINMUX('H', 6, AF11)>, /*ETH_MII_RXD2 */
81 <STM32_PINMUX('H', 7, AF11)>, /*ETH_MII_RXD3 */
82 <STM32_PINMUX('G',11, AF11)>, /*ETH_MII_TX_EN */
83 <STM32_PINMUX('C', 1, AF11)>, /*ETH_MII_MDC */
84 <STM32_PINMUX('A', 2, AF11)>; /*ETH_MII_MDIO */
Patrice Chotard01aabf92019-02-19 00:37:20 +010085 slew-rate = <2>;
86 };
87 };
88
89 fmc_pins: fmc@0 {
90 pins {
Patrice Chotardfe63d3c2019-02-19 16:49:05 +010091 pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
92 <STM32_PINMUX('I', 9, AF12)>, /* D30 */
93 <STM32_PINMUX('I', 7, AF12)>, /* D29 */
94 <STM32_PINMUX('I', 6, AF12)>, /* D28 */
95 <STM32_PINMUX('I', 3, AF12)>, /* D27 */
96 <STM32_PINMUX('I', 2, AF12)>, /* D26 */
97 <STM32_PINMUX('I', 1, AF12)>, /* D25 */
98 <STM32_PINMUX('I', 0, AF12)>, /* D24 */
99 <STM32_PINMUX('H',15, AF12)>, /* D23 */
100 <STM32_PINMUX('H',14, AF12)>, /* D22 */
101 <STM32_PINMUX('H',13, AF12)>, /* D21 */
102 <STM32_PINMUX('H',12, AF12)>, /* D20 */
103 <STM32_PINMUX('H',11, AF12)>, /* D19 */
104 <STM32_PINMUX('H',10, AF12)>, /* D18 */
105 <STM32_PINMUX('H', 9, AF12)>, /* D17 */
106 <STM32_PINMUX('H', 8, AF12)>, /* D16 */
Patrice Chotard01aabf92019-02-19 00:37:20 +0100107
Patrice Chotardfe63d3c2019-02-19 16:49:05 +0100108 <STM32_PINMUX('D',10, AF12)>, /* D15 */
109 <STM32_PINMUX('D', 9, AF12)>, /* D14 */
110 <STM32_PINMUX('D', 8, AF12)>, /* D13 */
111 <STM32_PINMUX('E',15, AF12)>, /* D12 */
112 <STM32_PINMUX('E',14, AF12)>, /* D11 */
113 <STM32_PINMUX('E',13, AF12)>, /* D10 */
114 <STM32_PINMUX('E',12, AF12)>, /* D9 */
115 <STM32_PINMUX('E',11, AF12)>, /* D8 */
116 <STM32_PINMUX('E',10, AF12)>, /* D7 */
117 <STM32_PINMUX('E', 9, AF12)>, /* D6 */
118 <STM32_PINMUX('E', 8, AF12)>, /* D5 */
119 <STM32_PINMUX('E', 7, AF12)>, /* D4 */
120 <STM32_PINMUX('D', 1, AF12)>, /* D3 */
121 <STM32_PINMUX('D', 0, AF12)>, /* D2 */
122 <STM32_PINMUX('D',15, AF12)>, /* D1 */
123 <STM32_PINMUX('D',14, AF12)>, /* D0 */
Patrice Chotard01aabf92019-02-19 00:37:20 +0100124
Patrice Chotardfe63d3c2019-02-19 16:49:05 +0100125 <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
126 <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
127 <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
128 <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
Patrice Chotard01aabf92019-02-19 00:37:20 +0100129
Patrice Chotardfe63d3c2019-02-19 16:49:05 +0100130 <STM32_PINMUX('G', 5, AF12)>, /* BA1 */
131 <STM32_PINMUX('G', 4, AF12)>, /* BA0 */
Patrice Chotard01aabf92019-02-19 00:37:20 +0100132
Patrice Chotardfe63d3c2019-02-19 16:49:05 +0100133 <STM32_PINMUX('G', 1, AF12)>, /* A11 */
134 <STM32_PINMUX('G', 0, AF12)>, /* A10 */
135 <STM32_PINMUX('F',15, AF12)>, /* A9 */
136 <STM32_PINMUX('F',14, AF12)>, /* A8 */
137 <STM32_PINMUX('F',13, AF12)>, /* A7 */
138 <STM32_PINMUX('F',12, AF12)>, /* A6 */
139 <STM32_PINMUX('F', 5, AF12)>, /* A5 */
140 <STM32_PINMUX('F', 4, AF12)>, /* A4 */
141 <STM32_PINMUX('F', 3, AF12)>, /* A3 */
142 <STM32_PINMUX('F', 2, AF12)>, /* A2 */
143 <STM32_PINMUX('F', 1, AF12)>, /* A1 */
144 <STM32_PINMUX('F', 0, AF12)>, /* A0 */
Patrice Chotard01aabf92019-02-19 00:37:20 +0100145
Patrice Chotardfe63d3c2019-02-19 16:49:05 +0100146 <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
147 <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
148 <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
149 <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
150 <STM32_PINMUX('C', 3, AF12)>, /* SDCKE0 */
151 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
Patrice Chotard01aabf92019-02-19 00:37:20 +0100152 slew-rate = <2>;
153 };
154 };
155
156 qspi_pins: qspi@0 {
157 pins {
Patrice Chotardfe63d3c2019-02-19 16:49:05 +0100158 pinmux = <STM32_PINMUX('B', 2, AF9)>, /* _FUNC_QUADSPI_CLK */
159 <STM32_PINMUX('B', 6, AF10)>, /*_FUNC_QUADSPI_BK1_NCS */
160 <STM32_PINMUX('F', 8, AF10)>, /* _FUNC_QUADSPI_BK1_IO0 */
161 <STM32_PINMUX('F', 9, AF10)>, /* _FUNC_QUADSPI_BK1_IO1 */
162 <STM32_PINMUX('F', 6, AF9)>, /* AF_FUNC_QUADSPI_BK1_IO3 */
163 <STM32_PINMUX('F', 7, AF9)>; /* _FUNC_QUADSPI_BK1_IO2 */
Patrice Chotard01aabf92019-02-19 00:37:20 +0100164 slew-rate = <2>;
165 };
166 };
Patrice Chotardfe63d3c2019-02-19 16:49:05 +0100167
168 usart1_pins_a: usart1@0 {
169 u-boot,dm-pre-reloc;
170 pins1 {
171 u-boot,dm-pre-reloc;
172 };
173 pins2 {
174 u-boot,dm-pre-reloc;
175 };
176 };
Patrice Chotard01aabf92019-02-19 00:37:20 +0100177};
178
179&qspi {
Patrice Chotardc987e082019-04-25 16:50:55 +0200180 reg = <0xA0001000 0x1000>, <0x90000000 0x4000000>;
Patrice Chotard01aabf92019-02-19 00:37:20 +0100181 qflash0: n25q512a {
182 #address-cells = <1>;
183 #size-cells = <1>;
184 spi-max-frequency = <108000000>;
185 spi-tx-bus-width = <1>;
186 spi-rx-bus-width = <1>;
187 reg = <0>;
188 };
189};