blob: 6787a6182c87a39d872ee8d29254ee470abcb4e0 [file] [log] [blame]
Chris Zankelc978b522016-08-10 18:36:44 +03001/*
2 * (C) Copyright 2008 - 2013 Tensilica Inc.
3 * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8/*
9 * CPU specific code
10 */
11
12#include <common.h>
13#include <command.h>
14#include <linux/stringify.h>
15#include <asm/global_data.h>
16#include <asm/cache.h>
17#include <asm/string.h>
18#include <asm/misc.h>
19
20DECLARE_GLOBAL_DATA_PTR;
21
22gd_t *gd __attribute__((section(".data")));
23
24#if defined(CONFIG_DISPLAY_CPUINFO)
25/*
26 * Print information about the CPU.
27 */
28
29int print_cpuinfo(void)
30{
31 char buf[120], mhz[8];
32 uint32_t id0, id1;
33
34 asm volatile ("rsr %0, 176\n"
35 "rsr %1, 208\n"
36 : "=r"(id0), "=r"(id1));
37
38 sprintf(buf, "CPU: Xtensa %s (id: %08x:%08x) at %s MHz\n",
39 XCHAL_CORE_ID, id0, id1, strmhz(mhz, gd->cpu_clk));
40 puts(buf);
41 return 0;
42}
43#endif
44
45int arch_cpu_init(void)
46{
47 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
48 return 0;
49}