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Tom Rini4549e782018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR X11
Mingkai Hudd029362016-09-07 18:47:28 +08002/*
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4 *
5 * Copyright (C) 2016, Freescale Semiconductor
6 *
7 * Mingkai Hu <mingkai.hu@nxp.com>
Mingkai Hudd029362016-09-07 18:47:28 +08008 */
9
10/include/ "skeleton64.dtsi"
11
12/ {
13 compatible = "fsl,ls1046a";
14 interrupt-parent = <&gic>;
15
16 sysclk: sysclk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <100000000>;
20 clock-output-names = "sysclk";
21 };
22
23 gic: interrupt-controller@1400000 {
24 compatible = "arm,gic-400";
25 #interrupt-cells = <3>;
26 interrupt-controller;
27 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
28 <0x0 0x1420000 0 0x10000>, /* GICC */
29 <0x0 0x1440000 0 0x20000>, /* GICH */
30 <0x0 0x1460000 0 0x20000>; /* GICV */
31 interrupts = <1 9 0xf08>;
32 };
33
34 soc {
35 compatible = "simple-bus";
36 #address-cells = <2>;
37 #size-cells = <2>;
38 ranges;
39
40 clockgen: clocking@1ee1000 {
41 compatible = "fsl,ls1046a-clockgen";
42 reg = <0x0 0x1ee1000 0x0 0x1000>;
43 #clock-cells = <2>;
44 clocks = <&sysclk>;
45 };
46
47 dspi0: dspi@2100000 {
48 compatible = "fsl,vf610-dspi";
49 #address-cells = <1>;
50 #size-cells = <0>;
51 reg = <0x0 0x2100000 0x0 0x10000>;
52 interrupts = <0 64 0x4>;
53 clock-names = "dspi";
54 clocks = <&clockgen 4 0>;
55 num-cs = <6>;
56 big-endian;
57 status = "disabled";
58 };
59
60 dspi1: dspi@2110000 {
61 compatible = "fsl,vf610-dspi";
62 #address-cells = <1>;
63 #size-cells = <0>;
64 reg = <0x0 0x2110000 0x0 0x10000>;
65 interrupts = <0 65 0x4>;
66 clock-names = "dspi";
67 clocks = <&clockgen 4 0>;
68 num-cs = <6>;
69 big-endian;
70 status = "disabled";
71 };
72
Yinbo Zhu2fd425f2018-09-25 14:47:11 +080073 esdhc: esdhc@1560000 {
74 compatible = "fsl,esdhc";
75 reg = <0x0 0x1560000 0x0 0x10000>;
76 interrupts = <0 62 0x4>;
77 big-endian;
78 bus-width = <4>;
79 };
80
Mingkai Hudd029362016-09-07 18:47:28 +080081 ifc: ifc@1530000 {
82 compatible = "fsl,ifc", "simple-bus";
83 reg = <0x0 0x1530000 0x0 0x10000>;
84 interrupts = <0 43 0x4>;
85 };
86
87 i2c0: i2c@2180000 {
88 compatible = "fsl,vf610-i2c";
89 #address-cells = <1>;
90 #size-cells = <0>;
91 reg = <0x0 0x2180000 0x0 0x10000>;
92 interrupts = <0 56 0x4>;
93 clock-names = "i2c";
94 clocks = <&clockgen 4 0>;
95 status = "disabled";
96 };
97
98 i2c1: i2c@2190000 {
99 compatible = "fsl,vf610-i2c";
100 #address-cells = <1>;
101 #size-cells = <0>;
102 reg = <0x0 0x2190000 0x0 0x10000>;
103 interrupts = <0 57 0x4>;
104 clock-names = "i2c";
105 clocks = <&clockgen 4 0>;
106 status = "disabled";
107 };
108
109 i2c2: i2c@21a0000 {
110 compatible = "fsl,vf610-i2c";
111 #address-cells = <1>;
112 #size-cells = <0>;
113 reg = <0x0 0x21a0000 0x0 0x10000>;
114 interrupts = <0 58 0x4>;
115 clock-names = "i2c";
116 clocks = <&clockgen 4 0>;
117 status = "disabled";
118 };
119
120 i2c3: i2c@21b0000 {
121 compatible = "fsl,vf610-i2c";
122 #address-cells = <1>;
123 #size-cells = <0>;
124 reg = <0x0 0x21b0000 0x0 0x10000>;
125 interrupts = <0 59 0x4>;
126 clock-names = "i2c";
127 clocks = <&clockgen 4 0>;
128 status = "disabled";
129 };
130
131 duart0: serial@21c0500 {
132 compatible = "fsl,ns16550", "ns16550a";
133 reg = <0x00 0x21c0500 0x0 0x100>;
134 interrupts = <0 54 0x4>;
135 clocks = <&clockgen 4 0>;
136 };
137
138 duart1: serial@21c0600 {
139 compatible = "fsl,ns16550", "ns16550a";
140 reg = <0x00 0x21c0600 0x0 0x100>;
141 interrupts = <0 54 0x4>;
142 clocks = <&clockgen 4 0>;
143 };
144
145 duart2: serial@21d0500 {
146 compatible = "fsl,ns16550", "ns16550a";
147 reg = <0x0 0x21d0500 0x0 0x100>;
148 interrupts = <0 55 0x4>;
149 clocks = <&clockgen 4 0>;
150 };
151
152 duart3: serial@21d0600 {
153 compatible = "fsl,ns16550", "ns16550a";
154 reg = <0x0 0x21d0600 0x0 0x100>;
155 interrupts = <0 55 0x4>;
156 clocks = <&clockgen 4 0>;
157 };
158
Shaohui Xiefdc2b542016-10-28 14:24:02 +0800159 lpuart0: serial@2950000 {
160 compatible = "fsl,ls1021a-lpuart";
161 reg = <0x0 0x2950000 0x0 0x1000>;
162 interrupts = <0 48 0x4>;
163 clocks = <&clockgen 4 0>;
164 clock-names = "ipg";
165 status = "disabled";
166 };
167
168 lpuart1: serial@2960000 {
169 compatible = "fsl,ls1021a-lpuart";
170 reg = <0x0 0x2960000 0x0 0x1000>;
171 interrupts = <0 49 0x4>;
172 clocks = <&clockgen 4 1>;
173 clock-names = "ipg";
174 status = "disabled";
175 };
176
177 lpuart2: serial@2970000 {
178 compatible = "fsl,ls1021a-lpuart";
179 reg = <0x0 0x2970000 0x0 0x1000>;
180 interrupts = <0 50 0x4>;
181 clocks = <&clockgen 4 1>;
182 clock-names = "ipg";
183 status = "disabled";
184 };
185
186 lpuart3: serial@2980000 {
187 compatible = "fsl,ls1021a-lpuart";
188 reg = <0x0 0x2980000 0x0 0x1000>;
189 interrupts = <0 51 0x4>;
190 clocks = <&clockgen 4 1>;
191 clock-names = "ipg";
192 status = "disabled";
193 };
194
195 lpuart4: serial@2990000 {
196 compatible = "fsl,ls1021a-lpuart";
197 reg = <0x0 0x2990000 0x0 0x1000>;
198 interrupts = <0 52 0x4>;
199 clocks = <&clockgen 4 1>;
200 clock-names = "ipg";
201 status = "disabled";
202 };
203
204 lpuart5: serial@29a0000 {
205 compatible = "fsl,ls1021a-lpuart";
206 reg = <0x0 0x29a0000 0x0 0x1000>;
207 interrupts = <0 53 0x4>;
208 clocks = <&clockgen 4 1>;
209 clock-names = "ipg";
210 status = "disabled";
211 };
212
Mingkai Hudd029362016-09-07 18:47:28 +0800213 qspi: quadspi@1550000 {
214 compatible = "fsl,vf610-qspi";
215 #address-cells = <1>;
216 #size-cells = <0>;
217 reg = <0x0 0x1550000 0x0 0x10000>,
218 <0x0 0x40000000 0x0 0x10000000>;
219 reg-names = "QuadSPI", "QuadSPI-memory";
220 num-cs = <4>;
221 big-endian;
222 status = "disabled";
223 };
Minghuan Lianb948a162016-12-13 14:54:14 +0800224
Tang Yuantian272a24f2017-01-20 17:12:48 +0800225 usb0: usb@2f00000 {
226 compatible = "fsl,layerscape-dwc3";
227 reg = <0x0 0x2f00000 0x0 0x10000>;
228 interrupts = <0 60 4>;
229 dr_mode = "host";
230 };
231
232 usb1: usb@3000000 {
233 compatible = "fsl,layerscape-dwc3";
234 reg = <0x0 0x3000000 0x0 0x10000>;
235 interrupts = <0 61 4>;
236 dr_mode = "host";
237 };
238
239 usb2: usb@3100000 {
240 compatible = "fsl,layerscape-dwc3";
241 reg = <0x0 0x3100000 0x0 0x10000>;
242 interrupts = <0 63 4>;
243 dr_mode = "host";
244 };
245
Minghuan Lianb948a162016-12-13 14:54:14 +0800246 pcie@3400000 {
247 compatible = "fsl,ls-pcie", "snps,dw-pcie";
248 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
249 0x00 0x03480000 0x0 0x40000 /* lut registers */
250 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
251 0x40 0x00000000 0x0 0x20000>; /* configuration space */
252 reg-names = "dbi", "lut", "ctrl", "config";
253 big-endian;
254 #address-cells = <3>;
255 #size-cells = <2>;
256 device_type = "pci";
257 bus-range = <0x0 0xff>;
258 ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000 /* downstream I/O */
259 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
260 };
261
262 pcie@3500000 {
263 compatible = "fsl,ls-pcie", "snps,dw-pcie";
264 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
265 0x00 0x03580000 0x0 0x40000 /* lut registers */
266 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
267 0x48 0x00000000 0x0 0x20000>; /* configuration space */
268 reg-names = "dbi", "lut", "ctrl", "config";
269 big-endian;
270 #address-cells = <3>;
271 #size-cells = <2>;
272 device_type = "pci";
273 num-lanes = <2>;
274 bus-range = <0x0 0xff>;
275 ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000 /* downstream I/O */
276 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
277 };
278
279 pcie@3600000 {
280 compatible = "fsl,ls-pcie", "snps,dw-pcie";
281 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
282 0x00 0x03680000 0x0 0x40000 /* lut registers */
283 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
284 0x50 0x00000000 0x0 0x20000>; /* configuration space */
285 reg-names = "dbi", "lut", "ctrl", "config";
286 big-endian;
287 #address-cells = <3>;
288 #size-cells = <2>;
289 device_type = "pci";
290 bus-range = <0x0 0xff>;
291 ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */
292 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
293 };
Peng Ma539e0cb2018-10-11 10:34:20 +0000294
295 sata: sata@3200000 {
296 compatible = "fsl,ls1046a-ahci";
Peng Mae765ee52019-04-17 10:10:49 +0000297 reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
298 0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/
299 reg-names = "sata-base", "ecc-addr";
Peng Ma539e0cb2018-10-11 10:34:20 +0000300 interrupts = <0 69 4>;
301 clocks = <&clockgen 4 1>;
302 status = "disabled";
303 };
Mingkai Hudd029362016-09-07 18:47:28 +0800304 };
305};