blob: 680f24c9c44d7cefaa219422535921bc897d7dde [file] [log] [blame]
Jagannadha Sutradharudu Teki9e0802b2014-01-09 01:48:29 +05301/*
2 * Xilinx ZC770 XM010 board DTS
3 *
Michal Simek5c45b162015-07-22 11:36:32 +02004 * Copyright (C) 2013 - 2015 Xilinx, Inc.
Jagannadha Sutradharudu Teki9e0802b2014-01-09 01:48:29 +05305 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8/dts-v1/;
9#include "zynq-7000.dtsi"
10
11/ {
Jagannadha Sutradharudu Teki9e0802b2014-01-09 01:48:29 +053012 compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
Michal Simek5c45b162015-07-22 11:36:32 +020013 model = "Xilinx Zynq";
Masahiro Yamada7d34c5d2014-05-15 20:37:54 +090014
Masahiro Yamada9f9d41b2014-05-15 20:37:55 +090015 aliases {
Michal Simek5c45b162015-07-22 11:36:32 +020016 ethernet0 = &gem0;
17 i2c0 = &i2c0;
Masahiro Yamada9f9d41b2014-05-15 20:37:55 +090018 serial0 = &uart1;
Michal Simek5c45b162015-07-22 11:36:32 +020019 spi0 = &spi1;
Masahiro Yamada9f9d41b2014-05-15 20:37:55 +090020 };
21
Michal Simek5c45b162015-07-22 11:36:32 +020022 chosen {
23 bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
24 linux,stdout-path = &uart1;
25 stdout-path = &uart1;
26 };
27
Michal Simekf0600af2015-08-12 11:25:05 +020028 memory {
Masahiro Yamada7d34c5d2014-05-15 20:37:54 +090029 device_type = "memory";
Michal Simek5c45b162015-07-22 11:36:32 +020030 reg = <0x0 0x40000000>;
31 };
32
33 usb_phy0: phy0 {
34 compatible = "usb-nop-xceiv";
35 #phy-cells = <0>;
Masahiro Yamada7d34c5d2014-05-15 20:37:54 +090036 };
Jagannadha Sutradharudu Teki9e0802b2014-01-09 01:48:29 +053037};
Jagan Teki89cab972015-06-27 00:51:35 +053038
39&spi1 {
40 status = "okay";
Michal Simek5c45b162015-07-22 11:36:32 +020041 num-cs = <4>;
42 is-decoded-cs = <0>;
43 flash@0 {
44 compatible = "sst25wf080";
45 reg = <1>;
46 spi-max-frequency = <1000000>;
47 #address-cells = <1>;
48 #size-cells = <1>;
49 partition@test {
50 label = "spi-flash";
51 reg = <0x0 0x100000>;
52 };
53 };
54};
55
56&can0 {
57 status = "okay";
58};
59
60&gem0 {
61 status = "okay";
62 phy-mode = "rgmii-id";
63 phy-handle = <&ethernet_phy>;
64
65 ethernet_phy: ethernet-phy@7 {
66 reg = <7>;
67 };
68};
69
70&i2c0 {
71 status = "okay";
72 clock-frequency = <400000>;
73
74 m24c02_eeprom@52 {
75 compatible = "at,24c02";
76 reg = <0x52>;
77 };
78
79};
80
81&sdhci0 {
82 status = "okay";
83};
84
85&uart1 {
86 status = "okay";
87};
88
89&usb0 {
90 status = "okay";
91 dr_mode = "host";
92 usb-phy = <&usb_phy0>;
Jagan Teki89cab972015-06-27 00:51:35 +053093};