blob: 2e694866e051948beb2302080bfee5cbd6ced8c7 [file] [log] [blame]
Giuseppe Pagano164d98462013-11-28 12:32:48 +01001/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <asm/imx-common/iomux-v3.h>
8#include <asm/arch/iomux.h>
9#include <asm/io.h>
Stefano Babicf5514e42013-12-19 11:04:33 +010010#include <asm/arch/clock.h>
Giuseppe Pagano164d98462013-11-28 12:32:48 +010011
12int setup_sata(void)
13{
14 struct iomuxc_base_regs *const iomuxc_regs
15 = (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
16
17 int ret = enable_sata_clock();
18 if (ret)
19 return ret;
20
21 clrsetbits_le32(&iomuxc_regs->gpr[13],
22 IOMUXC_GPR13_SATA_MASK,
23 IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
24 |IOMUXC_GPR13_SATA_PHY_7_SATA2M
25 |IOMUXC_GPR13_SATA_SPEED_3G
26 |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
27 |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
28 |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
29 |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
30 |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
31 |IOMUXC_GPR13_SATA_PHY_1_SLOW);
32
33 return 0;
34}