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stroeseb3182622003-09-12 08:41:56 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
26#include <command.h>
27#include <malloc.h>
28
29/* ------------------------------------------------------------------------- */
30
31#if 0
32#define FPGA_DEBUG
33#endif
34
35extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
36
37/* fpga configuration data - gzip compressed and generated by bin2c */
38const unsigned char fpgadata[] =
39{
40#include "fpgadata.c"
41};
42
43/*
44 * include common fpga code (for esd boards)
45 */
46#include "../common/fpga.c"
47
48
49/* Prototypes */
50int gunzip(void *, int, unsigned char *, int *);
51
52
wdenkc837dcb2004-01-20 23:12:12 +000053int board_early_init_f (void)
stroeseb3182622003-09-12 08:41:56 +000054{
55 /*
56 * IRQ 0-15 405GP internally generated; active high; level sensitive
57 * IRQ 16 405GP internally generated; active low; level sensitive
58 * IRQ 17-24 RESERVED
59 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
60 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
61 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
62 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
63 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
64 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
65 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
66 */
67 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
68 mtdcr(uicer, 0x00000000); /* disable all ints */
69 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
70 mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
71 mtdcr(uictr, 0x10000000); /* set int trigger levels */
72 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
73 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
74
75 /*
76 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
77 */
78 mtebc (epcr, 0xa8400000); /* ebc always driven */
79
80 return 0;
81}
82
83
84/* ------------------------------------------------------------------------- */
85
86int misc_init_f (void)
87{
88 return 0; /* dummy implementation */
89}
90
91
92int misc_init_r (void)
93{
94 volatile unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
95 volatile unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
96 unsigned char *dst;
97 ulong len = sizeof(fpgadata);
98 int status;
99 int index;
100 int i;
101
102#if 1 /* test-only */
103 dst = malloc(CFG_FPGA_MAX_SIZE);
104 if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
105 printf ("GUNZIP ERROR - must RESET board to recover\n");
106 do_reset (NULL, 0, 0, NULL);
107 }
108
109 status = fpga_boot(dst, len);
110 if (status != 0) {
111 printf("\nFPGA: Booting failed ");
112 switch (status) {
113 case ERROR_FPGA_PRG_INIT_LOW:
114 printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
115 break;
116 case ERROR_FPGA_PRG_INIT_HIGH:
117 printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
118 break;
119 case ERROR_FPGA_PRG_DONE:
120 printf("(Timeout: DONE not high after programming FPGA)\n ");
121 break;
122 }
123
124 /* display infos on fpgaimage */
125 index = 15;
126 for (i=0; i<4; i++) {
127 len = dst[index];
128 printf("FPGA: %s\n", &(dst[index+1]));
129 index += len+3;
130 }
131 putc ('\n');
132 /* delayed reboot */
133 for (i=20; i>0; i--) {
134 printf("Rebooting in %2d seconds \r",i);
135 for (index=0;index<1000;index++)
136 udelay(1000);
137 }
138 putc ('\n');
139 do_reset(NULL, 0, 0, NULL);
140 }
141
142 puts("FPGA: ");
143
144 /* display infos on fpgaimage */
145 index = 15;
146 for (i=0; i<4; i++) {
147 len = dst[index];
148 printf("%s ", &(dst[index+1]));
149 index += len+3;
150 }
151 putc ('\n');
152
153 free(dst);
154
155 /*
156 * Reset FPGA via FPGA_DATA pin
157 */
158 SET_FPGA(FPGA_PRG | FPGA_CLK);
159 udelay(1000); /* wait 1ms */
160 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
161 udelay(1000); /* wait 1ms */
162
163 /*
164 * Reset external DUARTs
165 */
166 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
167 udelay(10); /* wait 10us */
168 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
169 udelay(1000); /* wait 1ms */
170
171 /*
172 * Set NAND-FLASH GPIO signals to default
173 */
174 out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
175 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
176
177 /*
178 * Enable interrupts in exar duart mcr[3]
179 */
180 *duart0_mcr = 0x08;
181 *duart1_mcr = 0x08;
182#endif
183
184 return (0);
185}
186
187
188/*
189 * Check Board Identity:
190 */
191
192int checkboard (void)
193{
194 unsigned char str[64];
195 int i = getenv_r ("serial#", str, sizeof(str));
196
197 puts ("Board: ");
198
199 if (i == -1) {
200 puts ("### No HW ID - assuming PLU405");
201 } else {
202 puts(str);
203 }
204
205 putc ('\n');
206
207 return 0;
208}
209
210/* ------------------------------------------------------------------------- */
211
212long int initdram (int board_type)
213{
214 unsigned long val;
215
216 mtdcr(memcfga, mem_mb0cf);
217 val = mfdcr(memcfgd);
218
219#if 0
220 printf("\nmb0cf=%x\n", val); /* test-only */
221 printf("strap=%x\n", mfdcr(strap)); /* test-only */
222#endif
223
224 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
225}
226
227/* ------------------------------------------------------------------------- */
228
229int testdram (void)
230{
231 /* TODO: XXX XXX XXX */
232 printf ("test: 16 MB - ok\n");
233
234 return (0);
235}
236
237/* ------------------------------------------------------------------------- */
238
239#ifdef CONFIG_IDE_RESET
240void ide_set_reset(int on)
241{
242 volatile unsigned short *fpga_mode =
243 (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
244
245 /*
246 * Assert or deassert CompactFlash Reset Pin
247 */
248 if (on) { /* assert RESET */
249 *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
250 } else { /* release RESET */
251 *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
252 }
253}
254#endif /* CONFIG_IDE_RESET */
255
256
257#if (CONFIG_COMMANDS & CFG_CMD_NAND)
258#include <linux/mtd/nand.h>
259extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
260
261void nand_init(void)
262{
263 nand_probe(CFG_NAND_BASE);
264 if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
265 print_size(nand_dev_desc[0].totlen, "\n");
266 }
267}
268#endif