Sascha Hauer | 9b56f4f | 2008-03-26 20:40:42 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007 |
| 3 | * Sascha Hauer, Pengutronix |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | #include <common.h> |
| 25 | #include <asm/arch/mx31-regs.h> |
| 26 | |
| 27 | #define TIMER_BASE 0x53f90000 /* General purpose timer 1 */ |
| 28 | |
| 29 | /* General purpose timers registers */ |
| 30 | #define GPTCR __REG(TIMER_BASE) /* Control register */ |
| 31 | #define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */ |
| 32 | #define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */ |
| 33 | #define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */ |
| 34 | |
| 35 | /* General purpose timers bitfields */ |
| 36 | #define GPTCR_SWR (1<<15) /* Software reset */ |
| 37 | #define GPTCR_FRR (1<<9) /* Freerun / restart */ |
| 38 | #define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ |
| 39 | #define GPTCR_TEN (1) /* Timer enable */ |
| 40 | |
| 41 | /* nothing really to do with interrupts, just starts up a counter. */ |
| 42 | int interrupt_init (void) |
| 43 | { |
| 44 | int i; |
| 45 | |
| 46 | /* setup GP Timer 1 */ |
| 47 | GPTCR = GPTCR_SWR; |
| 48 | for ( i=0; i<100; i++) GPTCR = 0; /* We have no udelay by now */ |
| 49 | GPTPR = 0; /* 32Khz */ |
| 50 | GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */ |
| 51 | |
| 52 | return 0; |
| 53 | } |
| 54 | |
| 55 | void reset_timer_masked (void) |
| 56 | { |
| 57 | GPTCR = 0; |
| 58 | GPTCR = GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */ |
| 59 | } |
| 60 | |
| 61 | ulong get_timer_masked (void) |
| 62 | { |
| 63 | ulong val = GPTCNT; |
| 64 | return val; |
| 65 | } |
| 66 | |
| 67 | ulong get_timer (ulong base) |
| 68 | { |
| 69 | return get_timer_masked () - base; |
| 70 | } |
| 71 | |
| 72 | void set_timer (ulong t) |
| 73 | { |
| 74 | } |
| 75 | |
| 76 | /* delay x useconds AND perserve advance timstamp value */ |
| 77 | void udelay (unsigned long usec) |
| 78 | { |
| 79 | ulong tmo, tmp; |
| 80 | |
| 81 | if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ |
| 82 | tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ |
| 83 | tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ |
| 84 | tmo /= 1000; /* finish normalize. */ |
| 85 | } else { /* else small number, don't kill it prior to HZ multiply */ |
| 86 | tmo = usec * CFG_HZ; |
| 87 | tmo /= (1000*1000); |
| 88 | } |
| 89 | |
| 90 | tmp = get_timer (0); /* get current timestamp */ |
| 91 | if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */ |
| 92 | reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */ |
| 93 | else |
| 94 | tmo += tmp; /* else, set advancing stamp wake up time */ |
| 95 | while (get_timer_masked () < tmo)/* loop till event */ |
| 96 | /*NOP*/; |
| 97 | } |
| 98 | |
| 99 | void reset_cpu (ulong addr) |
| 100 | { |
| 101 | __REG16(WDOG_BASE) = 4; |
| 102 | } |