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Tim Harveyfe0f7f72014-06-02 16:13:23 -07001/*
2 * Copyright (C) 2014 Gateworks Corporation
3 * Author: Tim Harvey <tharvey@gateworks.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <linux/types.h>
10#include <asm/arch/mx6-ddr.h>
11#include <asm/arch/sys_proto.h>
12#include <asm/io.h>
13#include <asm/types.h>
14
15#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
16/* Configure MX6DQ mmdc iomux */
17void mx6dq_dram_iocfg(unsigned width,
18 const struct mx6dq_iomux_ddr_regs *ddr,
19 const struct mx6dq_iomux_grp_regs *grp)
20{
21 volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
22 volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
23
24 mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
25 mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
26
27 /* DDR IO Type */
28 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
29 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
30
31 /* Clock */
32 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
33 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
34
35 /* Address */
36 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
37 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
38 mx6_grp_iomux->grp_addds = grp->grp_addds;
39
40 /* Control */
41 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
42 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
43 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
44 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
45 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
46 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
47 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
48
49 /* Data Strobes */
50 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
51 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
52 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
53 if (width >= 32) {
54 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
55 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
56 }
57 if (width >= 64) {
58 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
59 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
60 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
61 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
62 }
63
64 /* Data */
65 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
66 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
67 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
68 if (width >= 32) {
69 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
70 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
71 }
72 if (width >= 64) {
73 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
74 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
75 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
76 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
77 }
78 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
79 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
80 if (width >= 32) {
81 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
82 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
83 }
84 if (width >= 64) {
85 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
86 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
87 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
88 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
89 }
90}
91#endif
92
93#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
94/* Configure MX6SDL mmdc iomux */
95void mx6sdl_dram_iocfg(unsigned width,
96 const struct mx6sdl_iomux_ddr_regs *ddr,
97 const struct mx6sdl_iomux_grp_regs *grp)
98{
99 volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
100 volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
101
102 mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
103 mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
104
105 /* DDR IO Type */
106 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
107 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
108
109 /* Clock */
110 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
111 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
112
113 /* Address */
114 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
115 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
116 mx6_grp_iomux->grp_addds = grp->grp_addds;
117
118 /* Control */
119 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
120 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
121 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
122 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
123 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
124 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
125 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
126
127 /* Data Strobes */
128 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
129 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
130 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
131 if (width >= 32) {
132 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
133 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
134 }
135 if (width >= 64) {
136 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
137 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
138 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
139 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
140 }
141
142 /* Data */
143 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
144 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
145 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
146 if (width >= 32) {
147 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
148 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
149 }
150 if (width >= 64) {
151 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
152 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
153 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
154 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
155 }
156 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
157 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
158 if (width >= 32) {
159 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
160 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
161 }
162 if (width >= 64) {
163 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
164 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
165 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
166 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
167 }
168}
169#endif
170
171/*
172 * Configure mx6 mmdc registers based on:
173 * - board-specific memory configuration
174 * - board-specific calibration data
175 * - ddr3 chip details
176 *
177 * The various calculations here are derived from the Freescale
178 * i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC
179 * configuration registers based on memory system and memory chip parameters.
180 *
181 * The defaults here are those which were specified in the spreadsheet.
182 * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
183 * section titled MMDC initialization
184 */
185#define MR(val, ba, cmd, cs1) \
186 ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
Nikita Kiryanov33689182014-09-07 18:58:11 +0300187void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
188 const struct mx6_mmdc_calibration *calib,
189 const struct mx6_ddr3_cfg *ddr3_cfg)
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700190{
191 volatile struct mmdc_p_regs *mmdc0;
192 volatile struct mmdc_p_regs *mmdc1;
Nikita Kiryanov33689182014-09-07 18:58:11 +0300193 u32 val;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700194 u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
195 u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
196 u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
197 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
Nikita Kiryanov33689182014-09-07 18:58:11 +0300198 u16 cs0_end;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700199 u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
Marek Vasutb299ab72014-08-04 01:47:10 +0200200 u8 coladdr;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700201 int clkper; /* clock period in picoseconds */
202 int clock; /* clock freq in mHz */
203 int cs;
204
205 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
206 mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
207
208 /* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
209 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
210 clock = 528;
211 tcwl = 4;
212 }
213 /* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */
214 else {
215 clock = 400;
216 tcwl = 3;
217 }
Nikita Kiryanov33689182014-09-07 18:58:11 +0300218 clkper = (1000 * 1000) / clock; /* pico seconds */
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700219 todtlon = tcwl;
220 taxpd = tcwl;
221 tanpd = tcwl;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700222
Nikita Kiryanov33689182014-09-07 18:58:11 +0300223 switch (ddr3_cfg->density) {
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700224 case 1: /* 1Gb per chip */
225 trfc = DIV_ROUND_UP(110000, clkper) - 1;
226 txs = DIV_ROUND_UP(120000, clkper) - 1;
227 break;
228 case 2: /* 2Gb per chip */
229 trfc = DIV_ROUND_UP(160000, clkper) - 1;
230 txs = DIV_ROUND_UP(170000, clkper) - 1;
231 break;
232 case 4: /* 4Gb per chip */
233 trfc = DIV_ROUND_UP(260000, clkper) - 1;
234 txs = DIV_ROUND_UP(270000, clkper) - 1;
235 break;
236 case 8: /* 8Gb per chip */
237 trfc = DIV_ROUND_UP(350000, clkper) - 1;
238 txs = DIV_ROUND_UP(360000, clkper) - 1;
239 break;
240 default:
241 /* invalid density */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300242 puts("invalid chip density\n");
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700243 hang();
244 break;
245 }
246 txpr = txs;
247
Nikita Kiryanov33689182014-09-07 18:58:11 +0300248 switch (ddr3_cfg->mem_speed) {
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700249 case 800:
Masahiro Yamadac79cba32014-09-18 13:28:06 +0900250 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
251 tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
Nikita Kiryanov33689182014-09-07 18:58:11 +0300252 if (ddr3_cfg->pagesz == 1) {
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700253 tfaw = DIV_ROUND_UP(40000, clkper) - 1;
Masahiro Yamadac79cba32014-09-18 13:28:06 +0900254 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700255 } else {
256 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
Masahiro Yamadac79cba32014-09-18 13:28:06 +0900257 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700258 }
259 break;
260 case 1066:
Masahiro Yamadac79cba32014-09-18 13:28:06 +0900261 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
262 tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
Nikita Kiryanov33689182014-09-07 18:58:11 +0300263 if (ddr3_cfg->pagesz == 1) {
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700264 tfaw = DIV_ROUND_UP(37500, clkper) - 1;
Masahiro Yamadac79cba32014-09-18 13:28:06 +0900265 trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700266 } else {
267 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
Masahiro Yamadac79cba32014-09-18 13:28:06 +0900268 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700269 }
270 break;
271 case 1333:
Masahiro Yamadac79cba32014-09-18 13:28:06 +0900272 txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1;
273 tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
Nikita Kiryanov33689182014-09-07 18:58:11 +0300274 if (ddr3_cfg->pagesz == 1) {
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700275 tfaw = DIV_ROUND_UP(30000, clkper) - 1;
Masahiro Yamadac79cba32014-09-18 13:28:06 +0900276 trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700277 } else {
278 tfaw = DIV_ROUND_UP(45000, clkper) - 1;
Masahiro Yamadac79cba32014-09-18 13:28:06 +0900279 trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700280 }
281 break;
282 case 1600:
Masahiro Yamadac79cba32014-09-18 13:28:06 +0900283 txp = DIV_ROUND_UP(max(3 * clkper, 6000), clkper) - 1;
284 tcke = DIV_ROUND_UP(max(3 * clkper, 5000), clkper) - 1;
Nikita Kiryanov33689182014-09-07 18:58:11 +0300285 if (ddr3_cfg->pagesz == 1) {
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700286 tfaw = DIV_ROUND_UP(30000, clkper) - 1;
Masahiro Yamadac79cba32014-09-18 13:28:06 +0900287 trrd = DIV_ROUND_UP(max(4 * clkper, 6000), clkper) - 1;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700288 } else {
289 tfaw = DIV_ROUND_UP(40000, clkper) - 1;
Masahiro Yamadac79cba32014-09-18 13:28:06 +0900290 trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700291 }
292 break;
293 default:
Nikita Kiryanov33689182014-09-07 18:58:11 +0300294 puts("invalid memory speed\n");
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700295 hang();
296 break;
297 }
Masahiro Yamadac79cba32014-09-18 13:28:06 +0900298 txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
299 tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700300 taonpd = DIV_ROUND_UP(2000, clkper) - 1;
Nikita Kiryanov33689182014-09-07 18:58:11 +0300301 tcksrx = tcksre;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700302 taofpd = taonpd;
Nikita Kiryanov33689182014-09-07 18:58:11 +0300303 twr = DIV_ROUND_UP(15000, clkper) - 1;
Masahiro Yamadac79cba32014-09-18 13:28:06 +0900304 tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
Nikita Kiryanov33689182014-09-07 18:58:11 +0300305 trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
306 tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
307 tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
308 trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
Masahiro Yamadac79cba32014-09-18 13:28:06 +0900309 twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700310 trcd = trp;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700311 trtp = twtr;
Nikita Kiryanov07ee9272014-08-20 15:08:58 +0300312 cs0_end = 4 * sysinfo->cs_density - 1;
Nikita Kiryanov33689182014-09-07 18:58:11 +0300313
314 debug("density:%d Gb (%d Gb per chip)\n",
315 sysinfo->cs_density, ddr3_cfg->density);
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700316 debug("clock: %dMHz (%d ps)\n", clock, clkper);
Nikita Kiryanov33689182014-09-07 18:58:11 +0300317 debug("memspd:%d\n", ddr3_cfg->mem_speed);
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700318 debug("tcke=%d\n", tcke);
319 debug("tcksrx=%d\n", tcksrx);
320 debug("tcksre=%d\n", tcksre);
321 debug("taofpd=%d\n", taofpd);
322 debug("taonpd=%d\n", taonpd);
323 debug("todtlon=%d\n", todtlon);
324 debug("tanpd=%d\n", tanpd);
325 debug("taxpd=%d\n", taxpd);
326 debug("trfc=%d\n", trfc);
327 debug("txs=%d\n", txs);
328 debug("txp=%d\n", txp);
329 debug("txpdll=%d\n", txpdll);
330 debug("tfaw=%d\n", tfaw);
331 debug("tcl=%d\n", tcl);
332 debug("trcd=%d\n", trcd);
333 debug("trp=%d\n", trp);
334 debug("trc=%d\n", trc);
335 debug("tras=%d\n", tras);
336 debug("twr=%d\n", twr);
337 debug("tmrd=%d\n", tmrd);
338 debug("tcwl=%d\n", tcwl);
339 debug("tdllk=%d\n", tdllk);
340 debug("trtp=%d\n", trtp);
341 debug("twtr=%d\n", twtr);
342 debug("trrd=%d\n", trrd);
343 debug("txpr=%d\n", txpr);
Nikita Kiryanov33689182014-09-07 18:58:11 +0300344 debug("cs0_end=%d\n", cs0_end);
345 debug("ncs=%d\n", sysinfo->ncs);
346 debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
347 debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
348 debug("SRT=%d\n", ddr3_cfg->SRT);
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700349 debug("tcl=%d\n", tcl);
350 debug("twr=%d\n", twr);
351
352 /*
353 * board-specific configuration:
354 * These values are determined empirically and vary per board layout
355 * see:
356 * appnote, ddr3 spreadsheet
357 */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300358 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
359 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
360 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
361 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
362 mmdc0->mprddlctl = calib->p0_mprddlctl;
363 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
364 if (sysinfo->dsize > 1) {
365 mmdc1->mpwldectrl0 = calib->p1_mpwldectrl0;
366 mmdc1->mpwldectrl1 = calib->p1_mpwldectrl1;
367 mmdc1->mpdgctrl0 = calib->p1_mpdgctrl0;
368 mmdc1->mpdgctrl1 = calib->p1_mpdgctrl1;
369 mmdc1->mprddlctl = calib->p1_mprddlctl;
370 mmdc1->mpwrdlctl = calib->p1_mpwrdlctl;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700371 }
372
373 /* Read data DQ Byte0-3 delay */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300374 mmdc0->mprddqby0dl = 0x33333333;
375 mmdc0->mprddqby1dl = 0x33333333;
376 if (sysinfo->dsize > 0) {
377 mmdc0->mprddqby2dl = 0x33333333;
378 mmdc0->mprddqby3dl = 0x33333333;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700379 }
Nikita Kiryanov33689182014-09-07 18:58:11 +0300380
381 if (sysinfo->dsize > 1) {
382 mmdc1->mprddqby0dl = 0x33333333;
383 mmdc1->mprddqby1dl = 0x33333333;
384 mmdc1->mprddqby2dl = 0x33333333;
385 mmdc1->mprddqby3dl = 0x33333333;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700386 }
387
388 /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300389 val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
390 mmdc0->mpodtctrl = val;
391 if (sysinfo->dsize > 1)
392 mmdc1->mpodtctrl = val;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700393
394 /* complete calibration */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300395 val = (1 << 11); /* Force measurement on delay-lines */
396 mmdc0->mpmur0 = val;
397 if (sysinfo->dsize > 1)
398 mmdc1->mpmur0 = val;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700399
400 /* Step 1: configuration request */
401 mmdc0->mdscr = (u32)(1 << 15); /* config request */
402
403 /* Step 2: Timing configuration */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300404 mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
405 (txpdll << 9) | (tfaw << 4) | tcl;
406 mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
407 (tras << 16) | (1 << 15) /* trpa */ |
408 (twr << 9) | (tmrd << 5) | tcwl;
409 mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
410 mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
411 (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
412 mmdc0->mdasp = cs0_end; /* CS addressing */
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700413
414 /* Step 3: Configure DDR type */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300415 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
416 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
417 (sysinfo->ralat << 6);
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700418
419 /* Step 4: Configure delay while leaving reset */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300420 mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
421 (sysinfo->rst_to_cke << 0);
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700422
423 /* Step 5: Configure DDR physical parameters (density and burst len) */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300424 coladdr = ddr3_cfg->coladdr;
425 if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
Marek Vasutb299ab72014-08-04 01:47:10 +0200426 coladdr += 4;
Nikita Kiryanov33689182014-09-07 18:58:11 +0300427 else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
Marek Vasutb299ab72014-08-04 01:47:10 +0200428 coladdr += 1;
Nikita Kiryanov33689182014-09-07 18:58:11 +0300429 mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
430 (coladdr - 9) << 20 | /* COL */
431 (1 << 19) | /* Burst Length = 8 for DDR3 */
432 (sysinfo->dsize << 16); /* DDR data bus size */
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700433
434 /* Step 6: Perform ZQ calibration */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300435 val = 0xa1390001; /* one-time HW ZQ calib */
436 mmdc0->mpzqhwctrl = val;
437 if (sysinfo->dsize > 1)
438 mmdc1->mpzqhwctrl = val;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700439
440 /* Step 7: Enable MMDC with desired chip select */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300441 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
442 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700443
444 /* Step 8: Write Mode Registers to Init DDR3 devices */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300445 for (cs = 0; cs < sysinfo->ncs; cs++) {
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700446 /* MR2 */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300447 val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700448 ((tcwl - 3) & 3) << 3;
Nikita Kiryanov33689182014-09-07 18:58:11 +0300449 mmdc0->mdscr = MR(val, 2, 3, cs);
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700450 /* MR3 */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300451 mmdc0->mdscr = MR(0, 3, 3, cs);
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700452 /* MR1 */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300453 val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
454 ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
455 mmdc0->mdscr = MR(val, 1, 3, cs);
456 /* MR0 */
457 val = ((tcl - 1) << 4) | /* CAS */
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700458 (1 << 8) | /* DLL Reset */
459 ((twr - 3) << 9); /* Write Recovery */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300460 mmdc0->mdscr = MR(val, 0, 3, cs);
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700461 /* ZQ calibration */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300462 val = (1 << 10);
463 mmdc0->mdscr = MR(val, 0, 4, cs);
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700464 }
465
466 /* Step 10: Power down control and self-refresh */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300467 mmdc0->mdpdc = (tcke & 0x7) << 16 |
468 5 << 12 | /* PWDT_1: 256 cycles */
469 5 << 8 | /* PWDT_0: 256 cycles */
Nikita Kiryanov08155282014-08-20 15:08:57 +0300470 1 << 7 | /* SLOW_PD */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300471 1 << 6 | /* BOTH_CS_PD */
472 (tcksrx & 0x7) << 3 |
473 (tcksre & 0x7);
Nikita Kiryanov06a51b82014-08-20 15:08:56 +0300474 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700475
476 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300477 val = 0xa1390003;
478 mmdc0->mpzqhwctrl = val;
479 if (sysinfo->dsize > 1)
480 mmdc1->mpzqhwctrl = val;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700481
482 /* Step 12: Configure and activate periodic refresh */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300483 mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
484 (7 << 11); /* REFR: Refresh Rate - 8 refreshes */
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700485
486 /* Step 13: Deassert config request - init complete */
Nikita Kiryanov33689182014-09-07 18:58:11 +0300487 mmdc0->mdscr = 0x00000000;
Tim Harveyfe0f7f72014-06-02 16:13:23 -0700488
489 /* wait for auto-ZQ calibration to complete */
490 mdelay(1);
491}