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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Alison Wang427eba72013-05-27 22:55:45 +00002/*
Vabhav Sharma1edc5682019-01-31 12:08:10 +00003 * Copyright 2019 NXP
Alison Wang427eba72013-05-27 22:55:45 +00004 * Copyright 2013 Freescale Semiconductor, Inc.
Alison Wang427eba72013-05-27 22:55:45 +00005 */
6
7#include <common.h>
Peng Fan8f5b6292018-10-19 00:26:23 +02008#include <clk.h>
Bin Mengfdbae092016-01-13 19:39:04 -08009#include <dm.h>
Peng Fanc40d6122017-02-22 16:21:51 +080010#include <fsl_lpuart.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060011#include <log.h>
Alison Wang427eba72013-05-27 22:55:45 +000012#include <watchdog.h>
13#include <asm/io.h>
14#include <serial.h>
Simon Glass336d4612020-02-03 07:36:16 -070015#include <dm/device_compat.h>
Simon Glasscd93d622020-05-10 11:40:13 -060016#include <linux/bitops.h>
Alison Wang427eba72013-05-27 22:55:45 +000017#include <linux/compiler.h>
18#include <asm/arch/imx-regs.h>
19#include <asm/arch/clock.h>
20
Bin Meng47f1bfc2016-01-13 19:39:01 -080021#define US1_TDRE (1 << 7)
22#define US1_RDRF (1 << 5)
23#define US1_OR (1 << 3)
24#define UC2_TE (1 << 3)
25#define UC2_RE (1 << 2)
26#define CFIFO_TXFLUSH (1 << 7)
27#define CFIFO_RXFLUSH (1 << 6)
28#define SFIFO_RXOF (1 << 2)
29#define SFIFO_RXUF (1 << 0)
Alison Wang427eba72013-05-27 22:55:45 +000030
Jingchang Lu6209e142014-09-05 13:52:47 +080031#define STAT_LBKDIF (1 << 31)
32#define STAT_RXEDGIF (1 << 30)
33#define STAT_TDRE (1 << 23)
34#define STAT_RDRF (1 << 21)
35#define STAT_IDLE (1 << 20)
36#define STAT_OR (1 << 19)
37#define STAT_NF (1 << 18)
38#define STAT_FE (1 << 17)
39#define STAT_PF (1 << 16)
40#define STAT_MA1F (1 << 15)
41#define STAT_MA2F (1 << 14)
42#define STAT_FLAGS (STAT_LBKDIF | STAT_RXEDGIF | STAT_IDLE | STAT_OR | \
Bin Meng47f1bfc2016-01-13 19:39:01 -080043 STAT_NF | STAT_FE | STAT_PF | STAT_MA1F | STAT_MA2F)
Jingchang Lu6209e142014-09-05 13:52:47 +080044
45#define CTRL_TE (1 << 19)
46#define CTRL_RE (1 << 18)
47
Ye Licdc16f62018-10-18 14:28:32 +020048#define FIFO_RXFLUSH BIT(14)
49#define FIFO_TXFLUSH BIT(15)
50#define FIFO_TXSIZE_MASK 0x70
51#define FIFO_TXSIZE_OFF 4
52#define FIFO_RXSIZE_MASK 0x7
53#define FIFO_RXSIZE_OFF 0
Jingchang Lu6209e142014-09-05 13:52:47 +080054#define FIFO_TXFE 0x80
Giulio Benettic32449a2020-01-10 15:51:43 +010055#if defined(CONFIG_ARCH_IMX8) || defined(CONFIG_ARCH_IMXRT)
Peng Fan126f8842018-10-18 14:28:31 +020056#define FIFO_RXFE 0x08
57#else
Jingchang Lu6209e142014-09-05 13:52:47 +080058#define FIFO_RXFE 0x40
Peng Fan126f8842018-10-18 14:28:31 +020059#endif
Jingchang Lu6209e142014-09-05 13:52:47 +080060
Ye Licdc16f62018-10-18 14:28:32 +020061#define WATER_TXWATER_OFF 0
Jingchang Lu6209e142014-09-05 13:52:47 +080062#define WATER_RXWATER_OFF 16
63
Alison Wang427eba72013-05-27 22:55:45 +000064DECLARE_GLOBAL_DATA_PTR;
65
Peng Fanc40d6122017-02-22 16:21:51 +080066#define LPUART_FLAG_REGMAP_32BIT_REG BIT(0)
67#define LPUART_FLAG_REGMAP_ENDIAN_BIG BIT(1)
68
Peng Fan7edf5c42017-02-22 16:21:52 +080069enum lpuart_devtype {
70 DEV_VF610 = 1,
71 DEV_LS1021A,
Peng Fan126f8842018-10-18 14:28:31 +020072 DEV_MX7ULP,
Giulio Benettic32449a2020-01-10 15:51:43 +010073 DEV_IMX8,
74 DEV_IMXRT,
Peng Fan7edf5c42017-02-22 16:21:52 +080075};
76
Bin Mengfdbae092016-01-13 19:39:04 -080077struct lpuart_serial_platdata {
Peng Fanc40d6122017-02-22 16:21:51 +080078 void *reg;
Peng Fan7edf5c42017-02-22 16:21:52 +080079 enum lpuart_devtype devtype;
Peng Fanc40d6122017-02-22 16:21:51 +080080 ulong flags;
Bin Mengfdbae092016-01-13 19:39:04 -080081};
82
Peng Fanc40d6122017-02-22 16:21:51 +080083static void lpuart_read32(u32 flags, u32 *addr, u32 *val)
Alison Wang427eba72013-05-27 22:55:45 +000084{
Peng Fanc40d6122017-02-22 16:21:51 +080085 if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
86 if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
87 *(u32 *)val = in_be32(addr);
88 else
89 *(u32 *)val = in_le32(addr);
90 }
91}
92
93static void lpuart_write32(u32 flags, u32 *addr, u32 val)
94{
95 if (flags & LPUART_FLAG_REGMAP_32BIT_REG) {
96 if (flags & LPUART_FLAG_REGMAP_ENDIAN_BIG)
97 out_be32(addr, val);
98 else
99 out_le32(addr, val);
100 }
101}
102
103
104#ifndef CONFIG_SYS_CLK_FREQ
105#define CONFIG_SYS_CLK_FREQ 0
106#endif
107
108u32 __weak get_lpuart_clk(void)
109{
110 return CONFIG_SYS_CLK_FREQ;
111}
112
Ye Liaf325e92019-07-11 03:33:34 +0000113#if CONFIG_IS_ENABLED(CLK)
Peng Fan8f5b6292018-10-19 00:26:23 +0200114static int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
115{
116 struct clk per_clk;
117 ulong rate;
118 int ret;
119
120 ret = clk_get_by_name(dev, "per", &per_clk);
121 if (ret) {
122 dev_err(dev, "Failed to get per clk: %d\n", ret);
123 return ret;
124 }
125
126 rate = clk_get_rate(&per_clk);
127 if ((long)rate <= 0) {
128 dev_err(dev, "Failed to get per clk rate: %ld\n", (long)rate);
129 return ret;
130 }
131 *clk = rate;
132 return 0;
133}
134#else
135static inline int get_lpuart_clk_rate(struct udevice *dev, u32 *clk)
136{ return -ENOSYS; }
137#endif
138
Peng Fanc40d6122017-02-22 16:21:51 +0800139static bool is_lpuart32(struct udevice *dev)
140{
Simon Glasscaa4daa2020-12-03 16:55:18 -0700141 struct lpuart_serial_platdata *plat = dev->plat;
Peng Fanc40d6122017-02-22 16:21:51 +0800142
143 return plat->flags & LPUART_FLAG_REGMAP_32BIT_REG;
144}
145
Peng Fan8f5b6292018-10-19 00:26:23 +0200146static void _lpuart_serial_setbrg(struct udevice *dev,
Peng Fanc40d6122017-02-22 16:21:51 +0800147 int baudrate)
148{
Simon Glassc69cda22020-12-03 16:55:20 -0700149 struct lpuart_serial_platdata *plat = dev_get_plat(dev);
Peng Fanc40d6122017-02-22 16:21:51 +0800150 struct lpuart_fsl *base = plat->reg;
Peng Fan8f5b6292018-10-19 00:26:23 +0200151 u32 clk;
Alison Wang427eba72013-05-27 22:55:45 +0000152 u16 sbr;
Peng Fan8f5b6292018-10-19 00:26:23 +0200153 int ret;
154
Ye Liaf325e92019-07-11 03:33:34 +0000155 if (CONFIG_IS_ENABLED(CLK)) {
Peng Fan8f5b6292018-10-19 00:26:23 +0200156 ret = get_lpuart_clk_rate(dev, &clk);
157 if (ret)
158 return;
159 } else {
160 clk = get_lpuart_clk();
161 }
Alison Wang427eba72013-05-27 22:55:45 +0000162
Bin Meng6ca13b12016-01-13 19:39:03 -0800163 sbr = (u16)(clk / (16 * baudrate));
Alison Wang427eba72013-05-27 22:55:45 +0000164
Bin Meng47f1bfc2016-01-13 19:39:01 -0800165 /* place adjustment later - n/32 BRFA */
Alison Wang427eba72013-05-27 22:55:45 +0000166 __raw_writeb(sbr >> 8, &base->ubdh);
167 __raw_writeb(sbr & 0xff, &base->ubdl);
168}
169
Peng Fanc40d6122017-02-22 16:21:51 +0800170static int _lpuart_serial_getc(struct lpuart_serial_platdata *plat)
Alison Wang427eba72013-05-27 22:55:45 +0000171{
Peng Fanc40d6122017-02-22 16:21:51 +0800172 struct lpuart_fsl *base = plat->reg;
Stefan Agnera3db78d2014-08-19 17:54:27 +0200173 while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
Alison Wang427eba72013-05-27 22:55:45 +0000174 WATCHDOG_RESET();
175
Stefan Agnera3db78d2014-08-19 17:54:27 +0200176 barrier();
Alison Wang427eba72013-05-27 22:55:45 +0000177
178 return __raw_readb(&base->ud);
179}
180
Peng Fanc40d6122017-02-22 16:21:51 +0800181static void _lpuart_serial_putc(struct lpuart_serial_platdata *plat,
182 const char c)
Alison Wang427eba72013-05-27 22:55:45 +0000183{
Peng Fanc40d6122017-02-22 16:21:51 +0800184 struct lpuart_fsl *base = plat->reg;
185
Alison Wang427eba72013-05-27 22:55:45 +0000186 while (!(__raw_readb(&base->us1) & US1_TDRE))
187 WATCHDOG_RESET();
188
189 __raw_writeb(c, &base->ud);
190}
191
Bin Meng47f1bfc2016-01-13 19:39:01 -0800192/* Test whether a character is in the RX buffer */
Peng Fanc40d6122017-02-22 16:21:51 +0800193static int _lpuart_serial_tstc(struct lpuart_serial_platdata *plat)
Alison Wang427eba72013-05-27 22:55:45 +0000194{
Peng Fanc40d6122017-02-22 16:21:51 +0800195 struct lpuart_fsl *base = plat->reg;
196
Alison Wang427eba72013-05-27 22:55:45 +0000197 if (__raw_readb(&base->urcfifo) == 0)
198 return 0;
199
200 return 1;
201}
202
203/*
204 * Initialise the serial port with the given baudrate. The settings
205 * are always 8 data bits, no parity, 1 stop bit, no start bits.
206 */
Peng Fan8f5b6292018-10-19 00:26:23 +0200207static int _lpuart_serial_init(struct udevice *dev)
Alison Wang427eba72013-05-27 22:55:45 +0000208{
Simon Glassc69cda22020-12-03 16:55:20 -0700209 struct lpuart_serial_platdata *plat = dev_get_plat(dev);
Peng Fanc40d6122017-02-22 16:21:51 +0800210 struct lpuart_fsl *base = (struct lpuart_fsl *)plat->reg;
Alison Wang427eba72013-05-27 22:55:45 +0000211 u8 ctrl;
212
213 ctrl = __raw_readb(&base->uc2);
214 ctrl &= ~UC2_RE;
215 ctrl &= ~UC2_TE;
216 __raw_writeb(ctrl, &base->uc2);
217
218 __raw_writeb(0, &base->umodem);
219 __raw_writeb(0, &base->uc1);
220
Stefan Agner89e69fd2014-08-19 17:54:28 +0200221 /* Disable FIFO and flush buffer */
222 __raw_writeb(0x0, &base->upfifo);
223 __raw_writeb(0x0, &base->utwfifo);
224 __raw_writeb(0x1, &base->urwfifo);
225 __raw_writeb(CFIFO_TXFLUSH | CFIFO_RXFLUSH, &base->ucfifo);
226
Alison Wang427eba72013-05-27 22:55:45 +0000227 /* provide data bits, parity, stop bit, etc */
Peng Fan8f5b6292018-10-19 00:26:23 +0200228 _lpuart_serial_setbrg(dev, gd->baudrate);
Alison Wang427eba72013-05-27 22:55:45 +0000229
230 __raw_writeb(UC2_RE | UC2_TE, &base->uc2);
231
232 return 0;
233}
234
Peng Fan8f5b6292018-10-19 00:26:23 +0200235static void _lpuart32_serial_setbrg_7ulp(struct udevice *dev,
Peng Fan7edf5c42017-02-22 16:21:52 +0800236 int baudrate)
237{
Simon Glassc69cda22020-12-03 16:55:20 -0700238 struct lpuart_serial_platdata *plat = dev_get_plat(dev);
Peng Fan7edf5c42017-02-22 16:21:52 +0800239 struct lpuart_fsl_reg32 *base = plat->reg;
240 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
Peng Fan8f5b6292018-10-19 00:26:23 +0200241 u32 clk;
242 int ret;
243
Ye Liaf325e92019-07-11 03:33:34 +0000244 if (CONFIG_IS_ENABLED(CLK)) {
Peng Fan8f5b6292018-10-19 00:26:23 +0200245 ret = get_lpuart_clk_rate(dev, &clk);
246 if (ret)
247 return;
248 } else {
249 clk = get_lpuart_clk();
250 }
Peng Fan7edf5c42017-02-22 16:21:52 +0800251
252 baud_diff = baudrate;
253 osr = 0;
254 sbr = 0;
255
256 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
257 tmp_sbr = (clk / (baudrate * tmp_osr));
258
259 if (tmp_sbr == 0)
260 tmp_sbr = 1;
261
262 /*calculate difference in actual buad w/ current values */
263 tmp_diff = (clk / (tmp_osr * tmp_sbr));
264 tmp_diff = tmp_diff - baudrate;
265
266 /* select best values between sbr and sbr+1 */
267 if (tmp_diff > (baudrate - (clk / (tmp_osr * (tmp_sbr + 1))))) {
268 tmp_diff = baudrate - (clk / (tmp_osr * (tmp_sbr + 1)));
269 tmp_sbr++;
270 }
271
272 if (tmp_diff <= baud_diff) {
273 baud_diff = tmp_diff;
274 osr = tmp_osr;
275 sbr = tmp_sbr;
276 }
277 }
278
279 /*
280 * TODO: handle buadrate outside acceptable rate
281 * if (baudDiff > ((config->baudRate_Bps / 100) * 3))
282 * {
283 * Unacceptable baud rate difference of more than 3%
284 * return kStatus_LPUART_BaudrateNotSupport;
285 * }
286 */
287 tmp = in_le32(&base->baud);
288
289 if ((osr > 3) && (osr < 8))
290 tmp |= LPUART_BAUD_BOTHEDGE_MASK;
291
292 tmp &= ~LPUART_BAUD_OSR_MASK;
293 tmp |= LPUART_BAUD_OSR(osr-1);
294
295 tmp &= ~LPUART_BAUD_SBR_MASK;
296 tmp |= LPUART_BAUD_SBR(sbr);
297
298 /* explicitly disable 10 bit mode & set 1 stop bit */
299 tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK);
300
301 out_le32(&base->baud, tmp);
302}
303
Peng Fan8f5b6292018-10-19 00:26:23 +0200304static void _lpuart32_serial_setbrg(struct udevice *dev,
Peng Fanc40d6122017-02-22 16:21:51 +0800305 int baudrate)
Bin Mengfdbae092016-01-13 19:39:04 -0800306{
Simon Glassc69cda22020-12-03 16:55:20 -0700307 struct lpuart_serial_platdata *plat = dev_get_plat(dev);
Peng Fanc40d6122017-02-22 16:21:51 +0800308 struct lpuart_fsl_reg32 *base = plat->reg;
Peng Fan8f5b6292018-10-19 00:26:23 +0200309 u32 clk;
Jingchang Lu6209e142014-09-05 13:52:47 +0800310 u32 sbr;
Peng Fan8f5b6292018-10-19 00:26:23 +0200311 int ret;
312
Ye Liaf325e92019-07-11 03:33:34 +0000313 if (CONFIG_IS_ENABLED(CLK)) {
Peng Fan8f5b6292018-10-19 00:26:23 +0200314 ret = get_lpuart_clk_rate(dev, &clk);
315 if (ret)
316 return;
317 } else {
318 clk = get_lpuart_clk();
319 }
Jingchang Lu6209e142014-09-05 13:52:47 +0800320
Bin Meng6ca13b12016-01-13 19:39:03 -0800321 sbr = (clk / (16 * baudrate));
Jingchang Lu6209e142014-09-05 13:52:47 +0800322
Bin Meng47f1bfc2016-01-13 19:39:01 -0800323 /* place adjustment later - n/32 BRFA */
Peng Fanc40d6122017-02-22 16:21:51 +0800324 lpuart_write32(plat->flags, &base->baud, sbr);
Jingchang Lu6209e142014-09-05 13:52:47 +0800325}
326
Peng Fanc40d6122017-02-22 16:21:51 +0800327static int _lpuart32_serial_getc(struct lpuart_serial_platdata *plat)
Jingchang Lu6209e142014-09-05 13:52:47 +0800328{
Peng Fanc40d6122017-02-22 16:21:51 +0800329 struct lpuart_fsl_reg32 *base = plat->reg;
Peng Fan7edf5c42017-02-22 16:21:52 +0800330 u32 stat, val;
Jingchang Lu6209e142014-09-05 13:52:47 +0800331
Peng Fanc40d6122017-02-22 16:21:51 +0800332 lpuart_read32(plat->flags, &base->stat, &stat);
333 while ((stat & STAT_RDRF) == 0) {
334 lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
335 WATCHDOG_RESET();
336 lpuart_read32(plat->flags, &base->stat, &stat);
337 }
338
Peng Fan7edf5c42017-02-22 16:21:52 +0800339 lpuart_read32(plat->flags, &base->data, &val);
Peng Fanc40d6122017-02-22 16:21:51 +0800340
Sriram Dasha2bbfc52018-01-10 11:57:14 +0530341 lpuart_read32(plat->flags, &base->stat, &stat);
342 if (stat & STAT_OR)
343 lpuart_write32(plat->flags, &base->stat, STAT_OR);
Peng Fan7edf5c42017-02-22 16:21:52 +0800344
345 return val & 0x3ff;
Peng Fanc40d6122017-02-22 16:21:51 +0800346}
347
348static void _lpuart32_serial_putc(struct lpuart_serial_platdata *plat,
349 const char c)
350{
351 struct lpuart_fsl_reg32 *base = plat->reg;
352 u32 stat;
353
Sriram Dasha2bbfc52018-01-10 11:57:14 +0530354 if (c == '\n')
355 serial_putc('\r');
Peng Fan7edf5c42017-02-22 16:21:52 +0800356
Peng Fanc40d6122017-02-22 16:21:51 +0800357 while (true) {
358 lpuart_read32(plat->flags, &base->stat, &stat);
359
360 if ((stat & STAT_TDRE))
361 break;
362
Jingchang Lu6209e142014-09-05 13:52:47 +0800363 WATCHDOG_RESET();
364 }
365
Peng Fanc40d6122017-02-22 16:21:51 +0800366 lpuart_write32(plat->flags, &base->data, c);
Jingchang Lu6209e142014-09-05 13:52:47 +0800367}
368
Bin Meng47f1bfc2016-01-13 19:39:01 -0800369/* Test whether a character is in the RX buffer */
Peng Fanc40d6122017-02-22 16:21:51 +0800370static int _lpuart32_serial_tstc(struct lpuart_serial_platdata *plat)
Jingchang Lu6209e142014-09-05 13:52:47 +0800371{
Peng Fanc40d6122017-02-22 16:21:51 +0800372 struct lpuart_fsl_reg32 *base = plat->reg;
373 u32 water;
374
375 lpuart_read32(plat->flags, &base->water, &water);
376
377 if ((water >> 24) == 0)
Jingchang Lu6209e142014-09-05 13:52:47 +0800378 return 0;
379
380 return 1;
381}
382
383/*
384 * Initialise the serial port with the given baudrate. The settings
385 * are always 8 data bits, no parity, 1 stop bit, no start bits.
386 */
Peng Fan8f5b6292018-10-19 00:26:23 +0200387static int _lpuart32_serial_init(struct udevice *dev)
Jingchang Lu6209e142014-09-05 13:52:47 +0800388{
Simon Glassc69cda22020-12-03 16:55:20 -0700389 struct lpuart_serial_platdata *plat = dev_get_plat(dev);
Peng Fanc40d6122017-02-22 16:21:51 +0800390 struct lpuart_fsl_reg32 *base = (struct lpuart_fsl_reg32 *)plat->reg;
Ye Licdc16f62018-10-18 14:28:32 +0200391 u32 val, tx_fifo_size;
Jingchang Lu6209e142014-09-05 13:52:47 +0800392
Ye Licdc16f62018-10-18 14:28:32 +0200393 lpuart_read32(plat->flags, &base->ctrl, &val);
394 val &= ~CTRL_RE;
395 val &= ~CTRL_TE;
396 lpuart_write32(plat->flags, &base->ctrl, val);
Jingchang Lu6209e142014-09-05 13:52:47 +0800397
Peng Fanc40d6122017-02-22 16:21:51 +0800398 lpuart_write32(plat->flags, &base->modir, 0);
Ye Licdc16f62018-10-18 14:28:32 +0200399
400 lpuart_read32(plat->flags, &base->fifo, &val);
401 tx_fifo_size = (val & FIFO_TXSIZE_MASK) >> FIFO_TXSIZE_OFF;
402 /* Set the TX water to half of FIFO size */
403 if (tx_fifo_size > 1)
404 tx_fifo_size = tx_fifo_size >> 1;
405
406 /* Set RX water to 0, to be triggered by any receive data */
407 lpuart_write32(plat->flags, &base->water,
408 (tx_fifo_size << WATER_TXWATER_OFF));
409
410 /* Enable TX and RX FIFO */
411 val |= (FIFO_TXFE | FIFO_RXFE | FIFO_TXFLUSH | FIFO_RXFLUSH);
412 lpuart_write32(plat->flags, &base->fifo, val);
Jingchang Lu6209e142014-09-05 13:52:47 +0800413
Peng Fanc40d6122017-02-22 16:21:51 +0800414 lpuart_write32(plat->flags, &base->match, 0);
Jingchang Lu6209e142014-09-05 13:52:47 +0800415
Giulio Benettic32449a2020-01-10 15:51:43 +0100416 if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
417 plat->devtype == DEV_IMXRT) {
Peng Fan8f5b6292018-10-19 00:26:23 +0200418 _lpuart32_serial_setbrg_7ulp(dev, gd->baudrate);
Peng Fan7edf5c42017-02-22 16:21:52 +0800419 } else {
420 /* provide data bits, parity, stop bit, etc */
Peng Fan8f5b6292018-10-19 00:26:23 +0200421 _lpuart32_serial_setbrg(dev, gd->baudrate);
Peng Fan7edf5c42017-02-22 16:21:52 +0800422 }
Jingchang Lu6209e142014-09-05 13:52:47 +0800423
Peng Fanc40d6122017-02-22 16:21:51 +0800424 lpuart_write32(plat->flags, &base->ctrl, CTRL_RE | CTRL_TE);
Jingchang Lu6209e142014-09-05 13:52:47 +0800425
426 return 0;
427}
428
Peng Fanc40d6122017-02-22 16:21:51 +0800429static int lpuart_serial_setbrg(struct udevice *dev, int baudrate)
Bin Mengfdbae092016-01-13 19:39:04 -0800430{
Simon Glassc69cda22020-12-03 16:55:20 -0700431 struct lpuart_serial_platdata *plat = dev_get_plat(dev);
Bin Mengfdbae092016-01-13 19:39:04 -0800432
Peng Fan7edf5c42017-02-22 16:21:52 +0800433 if (is_lpuart32(dev)) {
Giulio Benettic32449a2020-01-10 15:51:43 +0100434 if (plat->devtype == DEV_MX7ULP || plat->devtype == DEV_IMX8 ||
435 plat->devtype == DEV_IMXRT)
Peng Fan8f5b6292018-10-19 00:26:23 +0200436 _lpuart32_serial_setbrg_7ulp(dev, baudrate);
Peng Fan7edf5c42017-02-22 16:21:52 +0800437 else
Peng Fan8f5b6292018-10-19 00:26:23 +0200438 _lpuart32_serial_setbrg(dev, baudrate);
Peng Fan7edf5c42017-02-22 16:21:52 +0800439 } else {
Peng Fan8f5b6292018-10-19 00:26:23 +0200440 _lpuart_serial_setbrg(dev, baudrate);
Peng Fan7edf5c42017-02-22 16:21:52 +0800441 }
Bin Mengfdbae092016-01-13 19:39:04 -0800442
443 return 0;
444}
445
Peng Fanc40d6122017-02-22 16:21:51 +0800446static int lpuart_serial_getc(struct udevice *dev)
Bin Mengfdbae092016-01-13 19:39:04 -0800447{
Simon Glasscaa4daa2020-12-03 16:55:18 -0700448 struct lpuart_serial_platdata *plat = dev->plat;
Bin Mengfdbae092016-01-13 19:39:04 -0800449
Peng Fanc40d6122017-02-22 16:21:51 +0800450 if (is_lpuart32(dev))
451 return _lpuart32_serial_getc(plat);
452
453 return _lpuart_serial_getc(plat);
Bin Mengfdbae092016-01-13 19:39:04 -0800454}
455
Peng Fanc40d6122017-02-22 16:21:51 +0800456static int lpuart_serial_putc(struct udevice *dev, const char c)
Bin Mengfdbae092016-01-13 19:39:04 -0800457{
Simon Glasscaa4daa2020-12-03 16:55:18 -0700458 struct lpuart_serial_platdata *plat = dev->plat;
Bin Mengfdbae092016-01-13 19:39:04 -0800459
Peng Fanc40d6122017-02-22 16:21:51 +0800460 if (is_lpuart32(dev))
461 _lpuart32_serial_putc(plat, c);
462 else
463 _lpuart_serial_putc(plat, c);
Bin Mengfdbae092016-01-13 19:39:04 -0800464
465 return 0;
466}
467
Peng Fanc40d6122017-02-22 16:21:51 +0800468static int lpuart_serial_pending(struct udevice *dev, bool input)
Bin Mengfdbae092016-01-13 19:39:04 -0800469{
Simon Glasscaa4daa2020-12-03 16:55:18 -0700470 struct lpuart_serial_platdata *plat = dev->plat;
Bin Mengfdbae092016-01-13 19:39:04 -0800471 struct lpuart_fsl *reg = plat->reg;
Peng Fanc40d6122017-02-22 16:21:51 +0800472 struct lpuart_fsl_reg32 *reg32 = plat->reg;
473 u32 stat;
474
475 if (is_lpuart32(dev)) {
476 if (input) {
477 return _lpuart32_serial_tstc(plat);
478 } else {
479 lpuart_read32(plat->flags, &reg32->stat, &stat);
480 return stat & STAT_TDRE ? 0 : 1;
481 }
482 }
Bin Mengfdbae092016-01-13 19:39:04 -0800483
484 if (input)
Peng Fanc40d6122017-02-22 16:21:51 +0800485 return _lpuart_serial_tstc(plat);
Bin Mengfdbae092016-01-13 19:39:04 -0800486 else
Peng Fanc40d6122017-02-22 16:21:51 +0800487 return __raw_readb(&reg->us1) & US1_TDRE ? 0 : 1;
Bin Mengfdbae092016-01-13 19:39:04 -0800488}
489
Peng Fanc40d6122017-02-22 16:21:51 +0800490static int lpuart_serial_probe(struct udevice *dev)
Bin Mengfdbae092016-01-13 19:39:04 -0800491{
Giulio Benetti55631db2020-01-10 15:47:05 +0100492#if CONFIG_IS_ENABLED(CLK)
493 struct clk per_clk;
494 int ret;
495
496 ret = clk_get_by_name(dev, "per", &per_clk);
497 if (!ret) {
498 ret = clk_enable(&per_clk);
499 if (ret) {
500 dev_err(dev, "Failed to get per clk: %d\n", ret);
501 return ret;
502 }
503 } else {
Giulio Benetti289dd9f2020-01-31 14:39:47 +0100504 debug("%s: Failed to get per clk: %d\n", __func__, ret);
Giulio Benetti55631db2020-01-10 15:47:05 +0100505 }
506#endif
507
Peng Fanc40d6122017-02-22 16:21:51 +0800508 if (is_lpuart32(dev))
Peng Fan8f5b6292018-10-19 00:26:23 +0200509 return _lpuart32_serial_init(dev);
Peng Fanc40d6122017-02-22 16:21:51 +0800510 else
Peng Fan8f5b6292018-10-19 00:26:23 +0200511 return _lpuart_serial_init(dev);
Bin Mengfdbae092016-01-13 19:39:04 -0800512}
Alison Wang427eba72013-05-27 22:55:45 +0000513
Bin Mengfdbae092016-01-13 19:39:04 -0800514static int lpuart_serial_ofdata_to_platdata(struct udevice *dev)
515{
Simon Glasscaa4daa2020-12-03 16:55:18 -0700516 struct lpuart_serial_platdata *plat = dev->plat;
Peng Fan7edf5c42017-02-22 16:21:52 +0800517 const void *blob = gd->fdt_blob;
Simon Glassda409cc2017-05-17 17:18:09 -0600518 int node = dev_of_offset(dev);
Bin Mengfdbae092016-01-13 19:39:04 -0800519 fdt_addr_t addr;
520
Masahiro Yamada25484932020-07-17 14:36:48 +0900521 addr = dev_read_addr(dev);
Bin Mengfdbae092016-01-13 19:39:04 -0800522 if (addr == FDT_ADDR_T_NONE)
523 return -EINVAL;
524
Peng Fanc40d6122017-02-22 16:21:51 +0800525 plat->reg = (void *)addr;
526 plat->flags = dev_get_driver_data(dev);
Bin Mengfdbae092016-01-13 19:39:04 -0800527
Vabhav Sharma1edc5682019-01-31 12:08:10 +0000528 if (fdtdec_get_bool(blob, node, "little-endian"))
529 plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG;
530
Peng Fan7edf5c42017-02-22 16:21:52 +0800531 if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart"))
532 plat->devtype = DEV_LS1021A;
533 else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart"))
534 plat->devtype = DEV_MX7ULP;
535 else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart"))
536 plat->devtype = DEV_VF610;
Peng Fan126f8842018-10-18 14:28:31 +0200537 else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart"))
538 plat->devtype = DEV_IMX8;
Giulio Benettic32449a2020-01-10 15:51:43 +0100539 else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart"))
540 plat->devtype = DEV_IMXRT;
Peng Fan7edf5c42017-02-22 16:21:52 +0800541
Bin Mengfdbae092016-01-13 19:39:04 -0800542 return 0;
543}
544
Bin Mengfdbae092016-01-13 19:39:04 -0800545static const struct dm_serial_ops lpuart_serial_ops = {
546 .putc = lpuart_serial_putc,
547 .pending = lpuart_serial_pending,
548 .getc = lpuart_serial_getc,
549 .setbrg = lpuart_serial_setbrg,
550};
551
552static const struct udevice_id lpuart_serial_ids[] = {
Peng Fanc40d6122017-02-22 16:21:51 +0800553 { .compatible = "fsl,ls1021a-lpuart", .data =
554 LPUART_FLAG_REGMAP_32BIT_REG | LPUART_FLAG_REGMAP_ENDIAN_BIG },
Peng Fan7edf5c42017-02-22 16:21:52 +0800555 { .compatible = "fsl,imx7ulp-lpuart",
556 .data = LPUART_FLAG_REGMAP_32BIT_REG },
Peng Fanc40d6122017-02-22 16:21:51 +0800557 { .compatible = "fsl,vf610-lpuart"},
Peng Fan126f8842018-10-18 14:28:31 +0200558 { .compatible = "fsl,imx8qm-lpuart",
559 .data = LPUART_FLAG_REGMAP_32BIT_REG },
Giulio Benettic32449a2020-01-10 15:51:43 +0100560 { .compatible = "fsl,imxrt-lpuart",
561 .data = LPUART_FLAG_REGMAP_32BIT_REG },
Bin Mengfdbae092016-01-13 19:39:04 -0800562 { }
563};
564
565U_BOOT_DRIVER(serial_lpuart) = {
566 .name = "serial_lpuart",
567 .id = UCLASS_SERIAL,
568 .of_match = lpuart_serial_ids,
569 .ofdata_to_platdata = lpuart_serial_ofdata_to_platdata,
Simon Glasscaa4daa2020-12-03 16:55:18 -0700570 .plat_auto = sizeof(struct lpuart_serial_platdata),
Bin Mengfdbae092016-01-13 19:39:04 -0800571 .probe = lpuart_serial_probe,
572 .ops = &lpuart_serial_ops,
Bin Mengfdbae092016-01-13 19:39:04 -0800573};