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Syed Mohammed Khasimde701d12011-04-19 14:00:34 -05001/*
2 * (C) Copyright 2010
3 * Texas Instruments, <www.ti.com>
4 * Syed Mohammed Khasim <khasim@ti.com>
5 *
6 * Referred to Linux Kernel DSS driver files for OMAP3 by
7 * Tomi Valkeinen from drivers/video/omap2/dss/
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation's version 2 and any
15 * later version the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef DSS_H
29#define DSS_H
30
Jeroen Hofstee8da2efb2012-05-18 00:51:01 +000031/* DSS Base Registers */
Jeroen Hofsteed9c13aa2012-05-18 00:51:00 +000032#define OMAP3_DSS_BASE 0x48050000
33#define OMAP3_DISPC_BASE 0x48050400
Syed Mohammed Khasimde701d12011-04-19 14:00:34 -050034#define OMAP3_VENC_BASE 0x48050C00
35
36/* DSS Registers */
37struct dss_regs {
Jeroen Hofsteed9c13aa2012-05-18 00:51:00 +000038 u32 revision; /* 0x00 */
39 u8 res1[12]; /* 0x04 */
40 u32 sysconfig; /* 0x10 */
41 u32 sysstatus; /* 0x14 */
42 u32 irqstatus; /* 0x18 */
43 u8 res2[36]; /* 0x1C */
Syed Mohammed Khasimde701d12011-04-19 14:00:34 -050044 u32 control; /* 0x40 */
45 u32 sdi_control; /* 0x44 */
46 u32 pll_control; /* 0x48 */
47};
48
49/* DISPC Registers */
50struct dispc_regs {
Jeroen Hofsteed9c13aa2012-05-18 00:51:00 +000051 u32 revision; /* 0x00 */
52 u8 res1[12]; /* 0x04 */
53 u32 sysconfig; /* 0x10 */
54 u32 sysstatus; /* 0x14 */
55 u32 irqstatus; /* 0x18 */
56 u32 irqenable; /* 0x1C */
57 u8 res2[32]; /* 0x20 */
Syed Mohammed Khasimde701d12011-04-19 14:00:34 -050058 u32 control; /* 0x40 */
59 u32 config; /* 0x44 */
60 u32 reserve_2; /* 0x48 */
61 u32 default_color0; /* 0x4C */
62 u32 default_color1; /* 0x50 */
63 u32 trans_color0; /* 0x54 */
64 u32 trans_color1; /* 0x58 */
65 u32 line_status; /* 0x5C */
66 u32 line_number; /* 0x60 */
67 u32 timing_h; /* 0x64 */
68 u32 timing_v; /* 0x68 */
69 u32 pol_freq; /* 0x6C */
70 u32 divisor; /* 0x70 */
71 u32 global_alpha; /* 0x74 */
72 u32 size_dig; /* 0x78 */
73 u32 size_lcd; /* 0x7C */
Jeroen Hofsteed9c13aa2012-05-18 00:51:00 +000074 u32 gfx_ba0; /* 0x80 */
75 u32 gfx_ba1; /* 0x84 */
76 u32 gfx_position; /* 0x88 */
77 u32 gfx_size; /* 0x8C */
78 u8 unused[16]; /* 0x90 */
79 u32 gfx_attributes; /* 0xA0 */
80 u32 gfx_fifo_threshold; /* 0xA4 */
81 u32 gfx_fifo_size_status; /* 0xA8 */
82 u32 gfx_row_inc; /* 0xAC */
83 u32 gfx_pixel_inc; /* 0xB0 */
84 u32 gfx_window_skip; /* 0xB4 */
85 u32 gfx_table_ba; /* 0xB8 */
Syed Mohammed Khasimde701d12011-04-19 14:00:34 -050086};
87
88/* VENC Registers */
89struct venc_regs {
90 u32 rev_id; /* 0x00 */
91 u32 status; /* 0x04 */
92 u32 f_control; /* 0x08 */
93 u32 reserve_1; /* 0x0C */
94 u32 vidout_ctrl; /* 0x10 */
95 u32 sync_ctrl; /* 0x14 */
96 u32 reserve_2; /* 0x18 */
97 u32 llen; /* 0x1C */
98 u32 flens; /* 0x20 */
99 u32 hfltr_ctrl; /* 0x24 */
100 u32 cc_carr_wss_carr; /* 0x28 */
101 u32 c_phase; /* 0x2C */
102 u32 gain_u; /* 0x30 */
103 u32 gain_v; /* 0x34 */
104 u32 gain_y; /* 0x38 */
105 u32 black_level; /* 0x3C */
106 u32 blank_level; /* 0x40 */
107 u32 x_color; /* 0x44 */
108 u32 m_control; /* 0x48 */
109 u32 bstamp_wss_data; /* 0x4C */
110 u32 s_carr; /* 0x50 */
111 u32 line21; /* 0x54 */
112 u32 ln_sel; /* 0x58 */
113 u32 l21__wc_ctl; /* 0x5C */
114 u32 htrigger_vtrigger; /* 0x60 */
115 u32 savid__eavid; /* 0x64 */
116 u32 flen__fal; /* 0x68 */
117 u32 lal__phase_reset; /* 0x6C */
118 u32 hs_int_start_stop_x; /* 0x70 */
119 u32 hs_ext_start_stop_x; /* 0x74 */
120 u32 vs_int_start_x; /* 0x78 */
121 u32 vs_int_stop_x__vs_int_start_y; /* 0x7C */
122 u32 vs_int_stop_y__vs_ext_start_x; /* 0x80 */
123 u32 vs_ext_stop_x__vs_ext_start_y; /* 0x84 */
124 u32 vs_ext_stop_y; /* 0x88 */
125 u32 reserve_3; /* 0x8C */
126 u32 avid_start_stop_x; /* 0x90 */
127 u32 avid_start_stop_y; /* 0x94 */
128 u32 reserve_4; /* 0x98 */
129 u32 reserve_5; /* 0x9C */
130 u32 fid_int_start_x__fid_int_start_y; /* 0xA0 */
131 u32 fid_int_offset_y__fid_ext_start_x; /* 0xA4 */
132 u32 fid_ext_start_y__fid_ext_offset_y; /* 0xA8 */
133 u32 reserve_6; /* 0xAC */
134 u32 tvdetgp_int_start_stop_x; /* 0xB0 */
135 u32 tvdetgp_int_start_stop_y; /* 0xB4 */
136 u32 gen_ctrl; /* 0xB8 */
137 u32 reserve_7; /* 0xBC */
138 u32 reserve_8; /* 0xC0 */
139 u32 output_control; /* 0xC4 */
140 u32 dac_b__dac_c; /* 0xC8 */
141 u32 height_width; /* 0xCC */
142};
143
144/* Few Register Offsets */
Syed Mohammed Khasimde701d12011-04-19 14:00:34 -0500145#define TFTSTN_SHIFT 3
146#define DATALINES_SHIFT 8
147
Jeroen Hofsteed9c13aa2012-05-18 00:51:00 +0000148#define GFX_ENABLE 1
149#define GFX_FORMAT_SHIFT 1
150#define LOADMODE_SHIFT 1
151
152#define DSS_SOFTRESET (1 << 1)
153#define DSS_RESETDONE 1
154
Syed Mohammed Khasimde701d12011-04-19 14:00:34 -0500155/* Enabling Display controller */
156#define LCD_ENABLE 1
157#define DIG_ENABLE (1 << 1)
158#define GO_LCD (1 << 5)
159#define GO_DIG (1 << 6)
160#define GP_OUT0 (1 << 15)
161#define GP_OUT1 (1 << 16)
162
Syed Mohammed Khasimde701d12011-04-19 14:00:34 -0500163/* Configure VENC DSS Params */
164#define VENC_CLK_ENABLE (1 << 3)
165#define DAC_DEMEN (1 << 4)
166#define DAC_POWERDN (1 << 5)
167#define VENC_OUT_SEL (1 << 6)
168#define DIG_LPP_SHIFT 16
Jeroen Hofstee8da2efb2012-05-18 00:51:01 +0000169
Nikita Kiryanovbc84b182013-01-30 21:39:54 +0000170/* LCD display type */
171#define PASSIVE_DISPLAY 0
172#define ACTIVE_DISPLAY 1
173
174/* TFTDATALINES */
175#define LCD_INTERFACE_12_BIT 0
176#define LCD_INTERFACE_16_BIT 1
177#define LCD_INTERFACE_18_BIT 2
178#define LCD_INTERFACE_24_BIT 3
179
180/* Polarity */
Nikita Kiryanovf109a6e2013-10-16 17:23:28 +0300181#define DSS_IVS (1 << 12)
182#define DSS_IHS (1 << 13)
183#define DSS_IPC (1 << 14)
184#define DSS_IEO (1 << 15)
185#define DSS_ONOFF (1 << 17)
Nikita Kiryanovbc84b182013-01-30 21:39:54 +0000186
187/* GFX format */
188#define GFXFORMAT_BITMAP1 (0x0 << 1)
189#define GFXFORMAT_BITMAP2 (0x1 << 1)
190#define GFXFORMAT_BITMAP4 (0x2 << 1)
191#define GFXFORMAT_BITMAP8 (0x3 << 1)
192#define GFXFORMAT_RGB12 (0x4 << 1)
193#define GFXFORMAT_ARGB16 (0x5 << 1)
194#define GFXFORMAT_RGB16 (0x6 << 1)
195#define GFXFORMAT_RGB24_UNPACKED (0x8 << 1)
196#define GFXFORMAT_RGB24_PACKED (0x9 << 1)
197#define GFXFORMAT_ARGB32 (0xC << 1)
198#define GFXFORMAT_RGBA32 (0xD << 1)
199#define GFXFORMAT_RGBx32 (0xE << 1)
200
Jeroen Hofstee8da2efb2012-05-18 00:51:01 +0000201/* Panel Configuration */
Syed Mohammed Khasimde701d12011-04-19 14:00:34 -0500202struct panel_config {
203 u32 timing_h;
204 u32 timing_v;
205 u32 pol_freq;
206 u32 divisor;
207 u32 lcd_size;
208 u32 panel_type;
209 u32 data_lines;
210 u32 load_mode;
211 u32 panel_color;
Nikita Kiryanovbcc6cc92013-01-30 21:39:55 +0000212 u32 gfx_format;
Jeroen Hofsteed9c13aa2012-05-18 00:51:00 +0000213 void *frame_buffer;
Syed Mohammed Khasimde701d12011-04-19 14:00:34 -0500214};
215
Stefano Babicfb380bf2012-08-29 01:22:06 +0000216#define DSS_HBP(bp) (((bp) - 1) << 20)
217#define DSS_HFP(fp) (((fp) - 1) << 8)
218#define DSS_HSW(sw) ((sw) - 1)
219#define DSS_VBP(bp) ((bp) << 20)
220#define DSS_VFP(fp) ((fp) << 8)
221#define DSS_VSW(sw) ((sw) - 1)
222
223#define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw))
224#define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw))
Stefano Babic60c41d92012-10-16 04:07:05 +0000225#define PANEL_LCD_SIZE(xres, yres) ((yres - 1) << 16 | (xres - 1))
Stefano Babicfb380bf2012-08-29 01:22:06 +0000226
Jeroen Hofstee8da2efb2012-05-18 00:51:01 +0000227/* Generic DSS Functions */
Syed Mohammed Khasimde701d12011-04-19 14:00:34 -0500228void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
229 u32 height, u32 width);
230void omap3_dss_panel_config(const struct panel_config *panel_cfg);
231void omap3_dss_enable(void);
232
233#endif /* DSS_H */