blob: e2f7b53858a3cdb295cbd43706003dd2905d5e59 [file] [log] [blame]
Michal Simek44303df2015-10-30 15:39:18 +01001/*
2 * dts file for Xilinx ZynqMP
3 *
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10/ {
11 compatible = "xlnx,zynqmp";
12 #address-cells = <2>;
13 #size-cells = <1>;
14
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 compatible = "arm,cortex-a53", "arm,armv8";
21 device_type = "cpu";
22 enable-method = "psci";
23 reg = <0x0>;
24 };
25
26 cpu@1 {
27 compatible = "arm,cortex-a53", "arm,armv8";
28 device_type = "cpu";
29 enable-method = "psci";
30 reg = <0x1>;
31 };
32
33 cpu@2 {
34 compatible = "arm,cortex-a53", "arm,armv8";
35 device_type = "cpu";
36 enable-method = "psci";
37 reg = <0x2>;
38 };
39
40 cpu@3 {
41 compatible = "arm,cortex-a53", "arm,armv8";
42 device_type = "cpu";
43 enable-method = "psci";
44 reg = <0x3>;
45 };
46 };
47
Soren Brinkmann8f4e3972016-01-11 15:34:42 -080048 power-domains {
49 compatible = "xlnx,zynqmp-genpd";
50
51 pd_usb0: pd-usb0 {
52 #power-domain-cells = <0x0>;
53 pd-id = <0x16>;
54 };
55
56 pd_usb1: pd-usb1 {
57 #power-domain-cells = <0x0>;
58 pd-id = <0x17>;
59 };
60
61 pd_sata: pd-sata {
62 #power-domain-cells = <0x0>;
63 pd-id = <0x1c>;
64 };
65
66 pd_spi0: pd-spi0 {
67 #power-domain-cells = <0x0>;
68 pd-id = <0x23>;
69 };
70
71 pd_spi1: pd-spi1 {
72 #power-domain-cells = <0x0>;
73 pd-id = <0x24>;
74 };
75
76 pd_uart0: pd-uart0 {
77 #power-domain-cells = <0x0>;
78 pd-id = <0x21>;
79 };
80
81 pd_uart1: pd-uart1 {
82 #power-domain-cells = <0x0>;
83 pd-id = <0x22>;
84 };
85
86 pd_eth0: pd-eth0 {
87 #power-domain-cells = <0x0>;
88 pd-id = <0x1d>;
89 };
90
91 pd_eth1: pd-eth1 {
92 #power-domain-cells = <0x0>;
93 pd-id = <0x1e>;
94 };
95
96 pd_eth2: pd-eth2 {
97 #power-domain-cells = <0x0>;
98 pd-id = <0x1f>;
99 };
100
101 pd_eth3: pd-eth3 {
102 #power-domain-cells = <0x0>;
103 pd-id = <0x20>;
104 };
105
106 pd_i2c0: pd-i2c0 {
107 #power-domain-cells = <0x0>;
108 pd-id = <0x25>;
109 };
110
111 pd_i2c1: pd-i2c1 {
112 #power-domain-cells = <0x0>;
113 pd-id = <0x26>;
114 };
115
116 pd_dp: pd-dp {
117 /* fixme: what to attach to */
118 #power-domain-cells = <0x0>;
119 pd-id = <0x29>;
120 };
121
122 pd_gdma: pd-gdma {
123 #power-domain-cells = <0x0>;
124 pd-id = <0x2a>;
125 };
126
127 pd_adma: pd-adma {
128 #power-domain-cells = <0x0>;
129 pd-id = <0x2b>;
130 };
131
132 pd_ttc0: pd-ttc0 {
133 #power-domain-cells = <0x0>;
134 pd-id = <0x18>;
135 };
136
137 pd_ttc1: pd-ttc1 {
138 #power-domain-cells = <0x0>;
139 pd-id = <0x19>;
140 };
141
142 pd_ttc2: pd-ttc2 {
143 #power-domain-cells = <0x0>;
144 pd-id = <0x1a>;
145 };
146
147 pd_ttc3: pd-ttc3 {
148 #power-domain-cells = <0x0>;
149 pd-id = <0x1b>;
150 };
151
152 pd_sd0: pd-sd0 {
153 #power-domain-cells = <0x0>;
154 pd-id = <0x27>;
155 };
156
157 pd_sd1: pd-sd1 {
158 #power-domain-cells = <0x0>;
159 pd-id = <0x28>;
160 };
161
162 pd_nand: pd-nand {
163 #power-domain-cells = <0x0>;
164 pd-id = <0x2c>;
165 };
166
167 pd_qspi: pd-qspi {
168 #power-domain-cells = <0x0>;
169 pd-id = <0x2d>;
170 };
171
172 pd_gpio: pd-gpio {
173 #power-domain-cells = <0x0>;
174 pd-id = <0x2e>;
175 };
176
177 pd_can0: pd-can0 {
178 #power-domain-cells = <0x0>;
179 pd-id = <0x2f>;
180 };
181
182 pd_can1: pd-can1 {
183 #power-domain-cells = <0x0>;
184 pd-id = <0x30>;
185 };
186
187 pd_ddr: pd-ddr {
188 #power-domain-cells = <0x0>;
189 pd-id = <0x37>;
190 };
191
192 pd_apll: pd-apll {
193 #power-domain-cells = <0x0>;
194 pd-id = <0x32>;
195 };
196
197 pd_vpll: pd-vpll {
198 #power-domain-cells = <0x0>;
199 pd-id = <0x33>;
200 };
201
202 pd_dpll: pd-dpll {
203 #power-domain-cells = <0x0>;
204 pd-id = <0x34>;
205 };
206
207 pd_rpll: pd-rpll {
208 #power-domain-cells = <0x0>;
209 pd-id = <0x35>;
210 };
211
212 pd_iopll: pd-iopll {
213 #power-domain-cells = <0x0>;
214 pd-id = <0x36>;
215 };
216 };
217
Michal Simek44303df2015-10-30 15:39:18 +0100218 pmu {
219 compatible = "arm,armv8-pmuv3";
Michal Simek14cd9ea2016-04-07 15:28:33 +0200220 interrupt-parent = <&gic>;
Michal Simek44303df2015-10-30 15:39:18 +0100221 interrupts = <0 143 4>,
222 <0 144 4>,
223 <0 145 4>,
224 <0 146 4>;
225 };
226
227 psci {
228 compatible = "arm,psci-0.2";
229 method = "smc";
230 };
231
232 firmware {
233 compatible = "xlnx,zynqmp-pm";
234 method = "smc";
235 };
236
237 timer {
238 compatible = "arm,armv8-timer";
239 interrupt-parent = <&gic>;
240 interrupts = <1 13 0xf01>,
241 <1 14 0xf01>,
242 <1 11 0xf01>,
243 <1 10 0xf01>;
244 };
245
246 amba_apu: amba_apu {
247 compatible = "simple-bus";
248 #address-cells = <2>;
249 #size-cells = <1>;
250 ranges;
251
252 gic: interrupt-controller@f9010000 {
253 compatible = "arm,gic-400", "arm,cortex-a15-gic";
254 #interrupt-cells = <3>;
255 reg = <0x0 0xf9010000 0x10000>,
256 <0x0 0xf902f000 0x2000>,
257 <0x0 0xf9040000 0x20000>,
258 <0x0 0xf906f000 0x2000>;
259 interrupt-controller;
260 interrupt-parent = <&gic>;
261 interrupts = <1 9 0xf04>;
262 };
263 };
264
265 amba: amba {
266 compatible = "simple-bus";
267 #address-cells = <2>;
268 #size-cells = <1>;
269 ranges;
270
271 can0: can@ff060000 {
272 compatible = "xlnx,zynq-can-1.0";
273 status = "disabled";
274 clock-names = "can_clk", "pclk";
275 reg = <0x0 0xff060000 0x1000>;
276 interrupts = <0 23 4>;
277 interrupt-parent = <&gic>;
278 tx-fifo-depth = <0x40>;
279 rx-fifo-depth = <0x40>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800280 power-domains = <&pd_can0>;
Michal Simek44303df2015-10-30 15:39:18 +0100281 };
282
283 can1: can@ff070000 {
284 compatible = "xlnx,zynq-can-1.0";
285 status = "disabled";
286 clock-names = "can_clk", "pclk";
287 reg = <0x0 0xff070000 0x1000>;
288 interrupts = <0 24 4>;
289 interrupt-parent = <&gic>;
290 tx-fifo-depth = <0x40>;
291 rx-fifo-depth = <0x40>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800292 power-domains = <&pd_can1>;
Michal Simek44303df2015-10-30 15:39:18 +0100293 };
294
Michal Simekff50d212015-11-26 11:21:25 +0100295 cci: cci@fd6e0000 {
296 compatible = "arm,cci-400";
297 reg = <0x0 0xfd6e0000 0x9000>;
298 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
299 #address-cells = <1>;
300 #size-cells = <1>;
301
302 pmu@9000 {
303 compatible = "arm,cci-400-pmu,r1";
304 reg = <0x9000 0x5000>;
305 interrupt-parent = <&gic>;
306 interrupts = <0 123 4>,
307 <0 123 4>,
308 <0 123 4>,
309 <0 123 4>,
310 <0 123 4>;
311 };
312 };
313
Michal Simek44303df2015-10-30 15:39:18 +0100314 /* GDMA */
315 fpd_dma_chan1: dma@fd500000 {
316 status = "disabled";
317 compatible = "xlnx,zynqmp-dma-1.0";
318 reg = <0x0 0xfd500000 0x1000>;
319 interrupt-parent = <&gic>;
320 interrupts = <0 124 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530321 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100322 xlnx,id = <0>;
323 xlnx,bus-width = <128>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800324 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100325 };
326
327 fpd_dma_chan2: dma@fd510000 {
328 status = "disabled";
329 compatible = "xlnx,zynqmp-dma-1.0";
330 reg = <0x0 0xfd510000 0x1000>;
331 interrupt-parent = <&gic>;
332 interrupts = <0 125 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530333 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100334 xlnx,id = <1>;
335 xlnx,bus-width = <128>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800336 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100337 };
338
339 fpd_dma_chan3: dma@fd520000 {
340 status = "disabled";
341 compatible = "xlnx,zynqmp-dma-1.0";
342 reg = <0x0 0xfd520000 0x1000>;
343 interrupt-parent = <&gic>;
344 interrupts = <0 126 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530345 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100346 xlnx,id = <2>;
347 xlnx,bus-width = <128>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800348 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100349 };
350
351 fpd_dma_chan4: dma@fd530000 {
352 status = "disabled";
353 compatible = "xlnx,zynqmp-dma-1.0";
354 reg = <0x0 0xfd530000 0x1000>;
355 interrupt-parent = <&gic>;
356 interrupts = <0 127 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530357 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100358 xlnx,id = <3>;
359 xlnx,bus-width = <128>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800360 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100361 };
362
363 fpd_dma_chan5: dma@fd540000 {
364 status = "disabled";
365 compatible = "xlnx,zynqmp-dma-1.0";
366 reg = <0x0 0xfd540000 0x1000>;
367 interrupt-parent = <&gic>;
368 interrupts = <0 128 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530369 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100370 xlnx,id = <4>;
371 xlnx,bus-width = <128>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800372 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100373 };
374
375 fpd_dma_chan6: dma@fd550000 {
376 status = "disabled";
377 compatible = "xlnx,zynqmp-dma-1.0";
378 reg = <0x0 0xfd550000 0x1000>;
379 interrupt-parent = <&gic>;
380 interrupts = <0 129 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530381 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100382 xlnx,id = <5>;
383 xlnx,bus-width = <128>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800384 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100385 };
386
387 fpd_dma_chan7: dma@fd560000 {
388 status = "disabled";
389 compatible = "xlnx,zynqmp-dma-1.0";
390 reg = <0x0 0xfd560000 0x1000>;
391 interrupt-parent = <&gic>;
392 interrupts = <0 130 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530393 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100394 xlnx,id = <6>;
395 xlnx,bus-width = <128>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800396 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100397 };
398
399 fpd_dma_chan8: dma@fd570000 {
400 status = "disabled";
401 compatible = "xlnx,zynqmp-dma-1.0";
402 reg = <0x0 0xfd570000 0x1000>;
403 interrupt-parent = <&gic>;
404 interrupts = <0 131 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530405 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100406 xlnx,id = <7>;
407 xlnx,bus-width = <128>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800408 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100409 };
410
411 gpu: gpu@fd4b0000 {
412 status = "disabled";
413 compatible = "arm,mali-400", "arm,mali-utgard";
414 reg = <0x0 0xfd4b0000 0x30000>;
415 interrupt-parent = <&gic>;
416 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
417 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
418 };
419
420 /* ADMA */
421 lpd_dma_chan1: dma@ffa80000 {
422 status = "disabled";
423 compatible = "xlnx,zynqmp-dma-1.0";
424 reg = <0x0 0xffa80000 0x1000>;
425 interrupt-parent = <&gic>;
426 interrupts = <0 77 4>;
427 xlnx,id = <0>;
428 xlnx,bus-width = <64>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800429 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100430 };
431
432 lpd_dma_chan2: dma@ffa90000 {
433 status = "disabled";
434 compatible = "xlnx,zynqmp-dma-1.0";
435 reg = <0x0 0xffa90000 0x1000>;
436 interrupt-parent = <&gic>;
437 interrupts = <0 78 4>;
438 xlnx,id = <1>;
439 xlnx,bus-width = <64>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800440 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100441 };
442
443 lpd_dma_chan3: dma@ffaa0000 {
444 status = "disabled";
445 compatible = "xlnx,zynqmp-dma-1.0";
446 reg = <0x0 0xffaa0000 0x1000>;
447 interrupt-parent = <&gic>;
448 interrupts = <0 79 4>;
449 xlnx,id = <2>;
450 xlnx,bus-width = <64>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800451 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100452 };
453
454 lpd_dma_chan4: dma@ffab0000 {
455 status = "disabled";
456 compatible = "xlnx,zynqmp-dma-1.0";
457 reg = <0x0 0xffab0000 0x1000>;
458 interrupt-parent = <&gic>;
459 interrupts = <0 80 4>;
460 xlnx,id = <3>;
461 xlnx,bus-width = <64>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800462 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100463 };
464
465 lpd_dma_chan5: dma@ffac0000 {
466 status = "disabled";
467 compatible = "xlnx,zynqmp-dma-1.0";
468 reg = <0x0 0xffac0000 0x1000>;
469 interrupt-parent = <&gic>;
470 interrupts = <0 81 4>;
471 xlnx,id = <4>;
472 xlnx,bus-width = <64>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800473 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100474 };
475
476 lpd_dma_chan6: dma@ffad0000 {
477 status = "disabled";
478 compatible = "xlnx,zynqmp-dma-1.0";
479 reg = <0x0 0xffad0000 0x1000>;
480 interrupt-parent = <&gic>;
481 interrupts = <0 82 4>;
482 xlnx,id = <5>;
483 xlnx,bus-width = <64>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800484 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100485 };
486
487 lpd_dma_chan7: dma@ffae0000 {
488 status = "disabled";
489 compatible = "xlnx,zynqmp-dma-1.0";
490 reg = <0x0 0xffae0000 0x1000>;
491 interrupt-parent = <&gic>;
492 interrupts = <0 83 4>;
493 xlnx,id = <6>;
494 xlnx,bus-width = <64>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800495 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100496 };
497
498 lpd_dma_chan8: dma@ffaf0000 {
499 status = "disabled";
500 compatible = "xlnx,zynqmp-dma-1.0";
501 reg = <0x0 0xffaf0000 0x1000>;
502 interrupt-parent = <&gic>;
503 interrupts = <0 84 4>;
504 xlnx,id = <7>;
505 xlnx,bus-width = <64>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800506 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100507 };
508
Naga Sureshkumar Relli90869002016-03-11 13:10:26 +0530509 mc: memory-controller@fd070000 {
510 compatible = "xlnx,zynqmp-ddrc-2.40a";
511 reg = <0x0 0xfd070000 0x30000>;
512 interrupt-parent = <&gic>;
513 interrupts = <0 112 4>;
514 };
515
Michal Simek44303df2015-10-30 15:39:18 +0100516 nand0: nand@ff100000 {
517 compatible = "arasan,nfc-v3p10";
518 status = "disabled";
519 reg = <0x0 0xff100000 0x1000>;
520 clock-names = "clk_sys", "clk_flash";
521 interrupt-parent = <&gic>;
522 interrupts = <0 14 4>;
523 #address-cells = <2>;
524 #size-cells = <1>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800525 power-domains = <&pd_nand>;
Michal Simek44303df2015-10-30 15:39:18 +0100526 };
527
528 gem0: ethernet@ff0b0000 {
Michal Simekda2ad782016-02-11 15:26:46 +0100529 compatible = "cdns,zynqmp-gem";
Michal Simek44303df2015-10-30 15:39:18 +0100530 status = "disabled";
531 interrupt-parent = <&gic>;
532 interrupts = <0 57 4>, <0 57 4>;
533 reg = <0x0 0xff0b0000 0x1000>;
534 clock-names = "pclk", "hclk", "tx_clk";
535 #address-cells = <1>;
536 #size-cells = <0>;
Edgar E. Iglesias7f1d7d92015-11-26 14:12:20 +0100537 #stream-id-cells = <1>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800538 power-domains = <&pd_eth0>;
Michal Simek44303df2015-10-30 15:39:18 +0100539 };
540
541 gem1: ethernet@ff0c0000 {
Michal Simekda2ad782016-02-11 15:26:46 +0100542 compatible = "cdns,zynqmp-gem";
Michal Simek44303df2015-10-30 15:39:18 +0100543 status = "disabled";
544 interrupt-parent = <&gic>;
545 interrupts = <0 59 4>, <0 59 4>;
546 reg = <0x0 0xff0c0000 0x1000>;
547 clock-names = "pclk", "hclk", "tx_clk";
548 #address-cells = <1>;
549 #size-cells = <0>;
Edgar E. Iglesias7f1d7d92015-11-26 14:12:20 +0100550 #stream-id-cells = <1>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800551 power-domains = <&pd_eth1>;
Michal Simek44303df2015-10-30 15:39:18 +0100552 };
553
554 gem2: ethernet@ff0d0000 {
Michal Simekda2ad782016-02-11 15:26:46 +0100555 compatible = "cdns,zynqmp-gem";
Michal Simek44303df2015-10-30 15:39:18 +0100556 status = "disabled";
557 interrupt-parent = <&gic>;
558 interrupts = <0 61 4>, <0 61 4>;
559 reg = <0x0 0xff0d0000 0x1000>;
560 clock-names = "pclk", "hclk", "tx_clk";
561 #address-cells = <1>;
562 #size-cells = <0>;
Edgar E. Iglesias7f1d7d92015-11-26 14:12:20 +0100563 #stream-id-cells = <1>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800564 power-domains = <&pd_eth2>;
Michal Simek44303df2015-10-30 15:39:18 +0100565 };
566
567 gem3: ethernet@ff0e0000 {
Michal Simekda2ad782016-02-11 15:26:46 +0100568 compatible = "cdns,zynqmp-gem";
Michal Simek44303df2015-10-30 15:39:18 +0100569 status = "disabled";
570 interrupt-parent = <&gic>;
571 interrupts = <0 63 4>, <0 63 4>;
572 reg = <0x0 0xff0e0000 0x1000>;
573 clock-names = "pclk", "hclk", "tx_clk";
574 #address-cells = <1>;
575 #size-cells = <0>;
Edgar E. Iglesias7f1d7d92015-11-26 14:12:20 +0100576 #stream-id-cells = <1>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800577 power-domains = <&pd_eth3>;
Michal Simek44303df2015-10-30 15:39:18 +0100578 };
579
580 gpio: gpio@ff0a0000 {
581 compatible = "xlnx,zynqmp-gpio-1.0";
582 status = "disabled";
583 #gpio-cells = <0x2>;
Michal Simek7c38ca32015-11-23 13:26:15 +0100584 #interrupt-cells = <2>;
585 interrupt-controller;
Michal Simek44303df2015-10-30 15:39:18 +0100586 interrupt-parent = <&gic>;
587 interrupts = <0 16 4>;
588 reg = <0x0 0xff0a0000 0x1000>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800589 power-domains = <&pd_gpio>;
Michal Simek44303df2015-10-30 15:39:18 +0100590 };
591
592 i2c0: i2c@ff020000 {
593 compatible = "cdns,i2c-r1p10";
594 status = "disabled";
595 interrupt-parent = <&gic>;
596 interrupts = <0 17 4>;
597 reg = <0x0 0xff020000 0x1000>;
598 #address-cells = <1>;
599 #size-cells = <0>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800600 power-domains = <&pd_i2c0>;
Michal Simek44303df2015-10-30 15:39:18 +0100601 };
602
603 i2c1: i2c@ff030000 {
604 compatible = "cdns,i2c-r1p10";
605 status = "disabled";
606 interrupt-parent = <&gic>;
607 interrupts = <0 18 4>;
608 reg = <0x0 0xff030000 0x1000>;
609 #address-cells = <1>;
610 #size-cells = <0>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800611 power-domains = <&pd_i2c1>;
Michal Simek44303df2015-10-30 15:39:18 +0100612 };
613
614 pcie: pcie@fd0e0000 {
615 compatible = "xlnx,nwl-pcie-2.11";
616 status = "disabled";
617 #address-cells = <3>;
618 #size-cells = <2>;
619 #interrupt-cells = <1>;
620 device_type = "pci";
621 interrupt-parent = <&gic>;
Michal Simek91a8b0e2016-01-20 12:59:23 +0100622 interrupts = <0 118 4>,
623 <0 116 4>,
624 <0 115 4>, /* MSI_1 [63...32] */
625 <0 114 4>; /* MSI_0 [31...0] */
Michal Simek44303df2015-10-30 15:39:18 +0100626 interrupt-names = "misc", "intx", "msi_1", "msi_0";
627 reg = <0x0 0xfd0e0000 0x1000>,
628 <0x0 0xfd480000 0x1000>,
629 <0x0 0xe0000000 0x1000000>;
630 reg-names = "breg", "pcireg", "cfg";
631 ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
Bharat Kumar Gogada33aec512016-02-15 21:18:58 +0530632 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
633 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
634 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
635 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
636 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
637 pcie_intc: legacy-interrupt-controller {
638 interrupt-controller;
639 #address-cells = <0>;
640 #interrupt-cells = <1>;
641 };
Michal Simek44303df2015-10-30 15:39:18 +0100642 };
643
644 qspi: spi@ff0f0000 {
645 compatible = "xlnx,zynqmp-qspi-1.0";
646 status = "disabled";
647 clock-names = "ref_clk", "pclk";
648 interrupts = <0 15 4>;
649 interrupt-parent = <&gic>;
650 num-cs = <1>;
Michal Simekc588d152016-04-07 15:01:33 +0200651 reg = <0x0 0xff0f0000 0x1000>,
652 <0x0 0xc0000000 0x8000000>;
Michal Simek44303df2015-10-30 15:39:18 +0100653 #address-cells = <1>;
654 #size-cells = <0>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800655 power-domains = <&pd_qspi>;
Michal Simek44303df2015-10-30 15:39:18 +0100656 };
657
658 rtc: rtc@ffa60000 {
659 compatible = "xlnx,zynqmp-rtc";
660 status = "disabled";
661 reg = <0x0 0xffa60000 0x100>;
662 interrupt-parent = <&gic>;
663 interrupts = <0 26 4>, <0 27 4>;
664 interrupt-names = "alarm", "sec";
665 };
666
667 sata: ahci@fd0c0000 {
668 compatible = "ceva,ahci-1v84";
669 status = "disabled";
670 reg = <0x0 0xfd0c0000 0x2000>;
671 interrupt-parent = <&gic>;
672 interrupts = <0 133 4>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800673 power-domains = <&pd_sata>;
Michal Simek44303df2015-10-30 15:39:18 +0100674 };
675
676 sdhci0: sdhci@ff160000 {
677 compatible = "arasan,sdhci-8.9a";
678 status = "disabled";
679 interrupt-parent = <&gic>;
680 interrupts = <0 48 4>;
681 reg = <0x0 0xff160000 0x1000>;
682 clock-names = "clk_xin", "clk_ahb";
P L Sai Krishnabd750e72016-01-19 19:01:10 +0530683 broken-tuning;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800684 power-domains = <&pd_sd0>;
Michal Simek44303df2015-10-30 15:39:18 +0100685 };
686
687 sdhci1: sdhci@ff170000 {
688 compatible = "arasan,sdhci-8.9a";
689 status = "disabled";
690 interrupt-parent = <&gic>;
691 interrupts = <0 49 4>;
692 reg = <0x0 0xff170000 0x1000>;
693 clock-names = "clk_xin", "clk_ahb";
P L Sai Krishnabd750e72016-01-19 19:01:10 +0530694 broken-tuning;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800695 power-domains = <&pd_sd1>;
Michal Simek44303df2015-10-30 15:39:18 +0100696 };
697
698 smmu: smmu@fd800000 {
699 compatible = "arm,mmu-500";
700 reg = <0x0 0xfd800000 0x20000>;
701 #global-interrupts = <1>;
702 interrupt-parent = <&gic>;
Edgar E. Iglesias88a85aa2015-11-26 14:12:19 +0100703 interrupts = <0 155 4>,
704 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
705 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
706 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
707 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
Edgar E. Iglesias7f1d7d92015-11-26 14:12:20 +0100708 mmu-masters = < &gem0 0x874
709 &gem1 0x875
710 &gem2 0x876
711 &gem3 0x877 >;
Michal Simek44303df2015-10-30 15:39:18 +0100712 };
713
714 spi0: spi@ff040000 {
715 compatible = "cdns,spi-r1p6";
716 status = "disabled";
717 interrupt-parent = <&gic>;
718 interrupts = <0 19 4>;
719 reg = <0x0 0xff040000 0x1000>;
720 clock-names = "ref_clk", "pclk";
721 #address-cells = <1>;
722 #size-cells = <0>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800723 power-domains = <&pd_spi0>;
Michal Simek44303df2015-10-30 15:39:18 +0100724 };
725
726 spi1: spi@ff050000 {
727 compatible = "cdns,spi-r1p6";
728 status = "disabled";
729 interrupt-parent = <&gic>;
730 interrupts = <0 20 4>;
731 reg = <0x0 0xff050000 0x1000>;
732 clock-names = "ref_clk", "pclk";
733 #address-cells = <1>;
734 #size-cells = <0>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800735 power-domains = <&pd_spi1>;
Michal Simek44303df2015-10-30 15:39:18 +0100736 };
737
738 ttc0: timer@ff110000 {
739 compatible = "cdns,ttc";
740 status = "disabled";
741 interrupt-parent = <&gic>;
742 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
743 reg = <0x0 0xff110000 0x1000>;
744 timer-width = <32>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800745 power-domains = <&pd_ttc0>;
Michal Simek44303df2015-10-30 15:39:18 +0100746 };
747
748 ttc1: timer@ff120000 {
749 compatible = "cdns,ttc";
750 status = "disabled";
751 interrupt-parent = <&gic>;
752 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
753 reg = <0x0 0xff120000 0x1000>;
754 timer-width = <32>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800755 power-domains = <&pd_ttc1>;
Michal Simek44303df2015-10-30 15:39:18 +0100756 };
757
758 ttc2: timer@ff130000 {
759 compatible = "cdns,ttc";
760 status = "disabled";
761 interrupt-parent = <&gic>;
762 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
763 reg = <0x0 0xff130000 0x1000>;
764 timer-width = <32>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800765 power-domains = <&pd_ttc2>;
Michal Simek44303df2015-10-30 15:39:18 +0100766 };
767
768 ttc3: timer@ff140000 {
769 compatible = "cdns,ttc";
770 status = "disabled";
771 interrupt-parent = <&gic>;
772 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
773 reg = <0x0 0xff140000 0x1000>;
774 timer-width = <32>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800775 power-domains = <&pd_ttc3>;
Michal Simek44303df2015-10-30 15:39:18 +0100776 };
777
778 uart0: serial@ff000000 {
Michal Simekca2f5872015-11-27 13:22:58 +0100779 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
Michal Simek44303df2015-10-30 15:39:18 +0100780 status = "disabled";
781 interrupt-parent = <&gic>;
782 interrupts = <0 21 4>;
783 reg = <0x0 0xff000000 0x1000>;
784 clock-names = "uart_clk", "pclk";
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800785 power-domains = <&pd_uart0>;
Michal Simek44303df2015-10-30 15:39:18 +0100786 };
787
788 uart1: serial@ff010000 {
Michal Simekca2f5872015-11-27 13:22:58 +0100789 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
Michal Simek44303df2015-10-30 15:39:18 +0100790 status = "disabled";
791 interrupt-parent = <&gic>;
792 interrupts = <0 22 4>;
793 reg = <0x0 0xff010000 0x1000>;
794 clock-names = "uart_clk", "pclk";
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800795 power-domains = <&pd_uart1>;
Michal Simek44303df2015-10-30 15:39:18 +0100796 };
797
798 usb0: usb@fe200000 {
799 compatible = "snps,dwc3";
800 status = "disabled";
801 interrupt-parent = <&gic>;
802 interrupts = <0 65 4>;
803 reg = <0x0 0xfe200000 0x40000>;
804 clock-names = "clk_xin", "clk_ahb";
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800805 power-domains = <&pd_usb0>;
Michal Simek44303df2015-10-30 15:39:18 +0100806 };
807
808 usb1: usb@fe300000 {
809 compatible = "snps,dwc3";
810 status = "disabled";
811 interrupt-parent = <&gic>;
812 interrupts = <0 70 4>;
813 reg = <0x0 0xfe300000 0x40000>;
814 clock-names = "clk_xin", "clk_ahb";
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800815 power-domains = <&pd_usb1>;
Michal Simek44303df2015-10-30 15:39:18 +0100816 };
817
818 watchdog0: watchdog@fd4d0000 {
819 compatible = "cdns,wdt-r1p2";
820 status = "disabled";
821 interrupt-parent = <&gic>;
Punnaiah Choudary Kallurid3fd4332015-11-04 12:34:17 +0530822 interrupts = <0 113 1>;
Michal Simek44303df2015-10-30 15:39:18 +0100823 reg = <0x0 0xfd4d0000 0x1000>;
824 timeout-sec = <10>;
825 };
826
827 xilinx_drm: xilinx_drm {
828 compatible = "xlnx,drm";
829 status = "disabled";
830 xlnx,encoder-slave = <&xlnx_dp>;
831 xlnx,connector-type = "DisplayPort";
832 xlnx,dp-sub = <&xlnx_dp_sub>;
833 planes {
834 xlnx,pixel-format = "rgb565";
835 plane0 {
836 dmas = <&xlnx_dpdma 3>;
837 dma-names = "dma";
838 };
839 plane1 {
840 dmas = <&xlnx_dpdma 0>;
841 dma-names = "dma";
842 };
843 };
844 };
845
Hyun Kwon695d75a2015-11-23 17:12:54 -0800846 xlnx_dp: dp@fd4a0000 {
Michal Simek44303df2015-10-30 15:39:18 +0100847 compatible = "xlnx,v-dp";
848 status = "disabled";
849 reg = <0x0 0xfd4a0000 0x1000>;
850 interrupts = <0 119 4>;
851 interrupt-parent = <&gic>;
852 clock-names = "aclk", "aud_clk";
853 xlnx,dp-version = "v1.2";
854 xlnx,max-lanes = <2>;
855 xlnx,max-link-rate = <540000>;
856 xlnx,max-bpc = <16>;
857 xlnx,enable-ycrcb;
858 xlnx,colormetry = "rgb";
859 xlnx,bpc = <8>;
860 xlnx,audio-chan = <2>;
861 xlnx,dp-sub = <&xlnx_dp_sub>;
Hyun Kwon939cfea2015-11-23 17:12:55 -0800862 xlnx,max-pclock-frequency = <300000>;
Michal Simek44303df2015-10-30 15:39:18 +0100863 };
864
865 xlnx_dp_snd_card: dp_snd_card {
866 compatible = "xlnx,dp-snd-card";
867 status = "disabled";
868 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
869 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
870 };
871
872 xlnx_dp_snd_codec0: dp_snd_codec0 {
873 compatible = "xlnx,dp-snd-codec";
874 status = "disabled";
875 clock-names = "aud_clk";
876 };
877
878 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
879 compatible = "xlnx,dp-snd-pcm";
880 status = "disabled";
881 dmas = <&xlnx_dpdma 4>;
882 dma-names = "tx";
883 };
884
885 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
886 compatible = "xlnx,dp-snd-pcm";
887 status = "disabled";
888 dmas = <&xlnx_dpdma 5>;
889 dma-names = "tx";
890 };
891
Hyun Kwon695d75a2015-11-23 17:12:54 -0800892 xlnx_dp_sub: dp_sub@fd4aa000 {
Michal Simek44303df2015-10-30 15:39:18 +0100893 compatible = "xlnx,dp-sub";
894 status = "disabled";
Michal Simekc588d152016-04-07 15:01:33 +0200895 reg = <0x0 0xfd4aa000 0x1000>,
896 <0x0 0xfd4ab000 0x1000>,
897 <0x0 0xfd4ac000 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100898 reg-names = "blend", "av_buf", "aud";
899 xlnx,output-fmt = "rgb";
Hyun Kwon939cfea2015-11-23 17:12:55 -0800900 xlnx,vid-fmt = "yuyv";
901 xlnx,gfx-fmt = "rgb565";
Michal Simek44303df2015-10-30 15:39:18 +0100902 };
903
904 xlnx_dpdma: dma@fd4c0000 {
905 compatible = "xlnx,dpdma";
906 status = "disabled";
907 reg = <0x0 0xfd4c0000 0x1000>;
908 interrupts = <0 122 4>;
909 interrupt-parent = <&gic>;
910 clock-names = "axi_clk";
911 dma-channels = <6>;
912 #dma-cells = <1>;
Michal Simek4e31d272016-01-27 19:04:56 +0100913 dma-video0channel@fd4c0000 {
Michal Simek44303df2015-10-30 15:39:18 +0100914 compatible = "xlnx,video0";
915 };
Michal Simek4e31d272016-01-27 19:04:56 +0100916 dma-video1channel@fd4c0000 {
Michal Simek44303df2015-10-30 15:39:18 +0100917 compatible = "xlnx,video1";
918 };
Michal Simek4e31d272016-01-27 19:04:56 +0100919 dma-video2channel@fd4c0000 {
Michal Simek44303df2015-10-30 15:39:18 +0100920 compatible = "xlnx,video2";
921 };
Michal Simek4e31d272016-01-27 19:04:56 +0100922 dma-graphicschannel@fd4c0000 {
Michal Simek44303df2015-10-30 15:39:18 +0100923 compatible = "xlnx,graphics";
924 };
Michal Simek4e31d272016-01-27 19:04:56 +0100925 dma-audio0channel@fd4c0000 {
Michal Simek44303df2015-10-30 15:39:18 +0100926 compatible = "xlnx,audio0";
927 };
Michal Simek4e31d272016-01-27 19:04:56 +0100928 dma-audio1channel@fd4c0000 {
Michal Simek44303df2015-10-30 15:39:18 +0100929 compatible = "xlnx,audio1";
930 };
931 };
932 };
933};