Reinhard Meyer | c7260d1 | 2010-07-27 16:22:09 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010 |
| 3 | * Reinhard Meyer, reinhard.meyer@emk-elektronik.de |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * Date & Time support for the internal Real-time Timer |
| 26 | * of AT91SAM9260 and compatibles. |
| 27 | * Compatible with the LinuX rtc driver workaround: |
| 28 | * The RTT cannot be written to, but only reset. |
| 29 | * The actual time is the sum of RTT and one of |
| 30 | * the four GPBR registers. |
| 31 | * |
| 32 | * The at91sam9260 has 4 GPBR (0-3). |
| 33 | * For their typical use see at91_gpbr.h ! |
| 34 | * |
| 35 | * make sure u-boot and kernel use the same GPBR ! |
| 36 | */ |
| 37 | |
| 38 | #include <common.h> |
| 39 | #include <command.h> |
| 40 | #include <rtc.h> |
Reinhard Meyer | 86592f6 | 2010-11-07 13:26:14 +0100 | [diff] [blame] | 41 | #include <asm/io.h> |
Reinhard Meyer | c7260d1 | 2010-07-27 16:22:09 +0200 | [diff] [blame] | 42 | #include <asm/errno.h> |
| 43 | #include <asm/arch/hardware.h> |
Reinhard Meyer | c7260d1 | 2010-07-27 16:22:09 +0200 | [diff] [blame] | 44 | #include <asm/arch/at91_rtt.h> |
| 45 | #include <asm/arch/at91_gpbr.h> |
| 46 | |
| 47 | #if defined(CONFIG_CMD_DATE) |
| 48 | |
| 49 | int rtc_get (struct rtc_time *tmp) |
| 50 | { |
Reinhard Meyer | 372f278 | 2010-11-03 15:47:20 +0100 | [diff] [blame] | 51 | at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT; |
| 52 | at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; |
Reinhard Meyer | c7260d1 | 2010-07-27 16:22:09 +0200 | [diff] [blame] | 53 | ulong tim; |
| 54 | ulong tim2; |
| 55 | ulong off; |
| 56 | |
| 57 | do { |
| 58 | tim = readl(&rtt->vr); |
| 59 | tim2 = readl(&rtt->vr); |
| 60 | } while (tim!=tim2); |
| 61 | off = readl(&gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); |
| 62 | /* off==0 means time is invalid, but we ignore that */ |
| 63 | to_tm (tim+off, tmp); |
| 64 | return 0; |
| 65 | } |
| 66 | |
| 67 | int rtc_set (struct rtc_time *tmp) |
| 68 | { |
Reinhard Meyer | 372f278 | 2010-11-03 15:47:20 +0100 | [diff] [blame] | 69 | at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT; |
| 70 | at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; |
Reinhard Meyer | c7260d1 | 2010-07-27 16:22:09 +0200 | [diff] [blame] | 71 | ulong tim; |
| 72 | |
| 73 | tim = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, |
| 74 | tmp->tm_hour, tmp->tm_min, tmp->tm_sec); |
| 75 | |
| 76 | /* clear alarm, set prescaler to 32768, clear counter */ |
| 77 | writel(32768+AT91_RTT_RTTRST, &rtt->mr); |
| 78 | writel(~0, &rtt->ar); |
| 79 | writel(tim, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); |
| 80 | /* wait for counter clear to happen, takes less than a 1/32768th second */ |
| 81 | while (readl(&rtt->vr) != 0) |
| 82 | ; |
| 83 | return 0; |
| 84 | } |
| 85 | |
| 86 | void rtc_reset (void) |
| 87 | { |
Reinhard Meyer | 372f278 | 2010-11-03 15:47:20 +0100 | [diff] [blame] | 88 | at91_rtt_t *rtt = (at91_rtt_t *) ATMEL_BASE_RTT; |
| 89 | at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; |
Reinhard Meyer | c7260d1 | 2010-07-27 16:22:09 +0200 | [diff] [blame] | 90 | |
| 91 | /* clear alarm, set prescaler to 32768, clear counter */ |
| 92 | writel(32768+AT91_RTT_RTTRST, &rtt->mr); |
| 93 | writel(~0, &rtt->ar); |
| 94 | writel(0, &gpbr->reg[AT91_GPBR_INDEX_TIMEOFF]); |
| 95 | /* wait for counter clear to happen, takes less than a 1/32768th second */ |
| 96 | while (readl(&rtt->vr) != 0) |
| 97 | ; |
| 98 | } |
| 99 | |
| 100 | #endif |