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wdenk42d1f032003-10-15 23:53:47 +00001/*
Dipen Dudhatbeba93e2011-01-19 12:46:27 +05302 * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
Kumar Gala39aaca12009-03-19 02:46:19 -05003 *
wdenk42d1f032003-10-15 23:53:47 +00004 * (C) Copyright 2003 Motorola Inc.
5 * Xianghua Xiao, (X.Xiao@motorola.com)
6 *
7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +000011 */
12
13#include <common.h>
14#include <ppc_asm.tmpl>
Haiying Wanga52d2f82011-02-11 01:25:30 -060015#include <linux/compiler.h>
wdenk42d1f032003-10-15 23:53:47 +000016#include <asm/processor.h>
Trent Piephoada591d2008-12-03 15:16:37 -080017#include <asm/io.h>
wdenk42d1f032003-10-15 23:53:47 +000018
Wolfgang Denkd87080b2006-03-31 18:32:53 +020019DECLARE_GLOBAL_DATA_PTR;
20
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +053021
22#ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
23#define CONFIG_SYS_FSL_NUM_CC_PLLS 6
24#endif
wdenk42d1f032003-10-15 23:53:47 +000025/* --------------------------------------------------------------- */
26
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +053027void get_sys_info(sys_info_t *sys_info)
wdenk42d1f032003-10-15 23:53:47 +000028{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Gala800c73c2012-10-08 07:44:06 +000030#ifdef CONFIG_FSL_IFC
31 struct fsl_ifc *ifc_regs = (void *)CONFIG_SYS_IFC_ADDR;
32 u32 ccr;
33#endif
Kumar Gala39aaca12009-03-19 02:46:19 -050034#ifdef CONFIG_FSL_CORENET
35 volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
Timur Tabifbb9ecf2011-08-05 16:15:24 -050036 unsigned int cpu;
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +053037#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
38 int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
39#endif
Kumar Gala39aaca12009-03-19 02:46:19 -050040
41 const u8 core_cplx_PLL[16] = {
42 [ 0] = 0, /* CC1 PPL / 1 */
43 [ 1] = 0, /* CC1 PPL / 2 */
44 [ 2] = 0, /* CC1 PPL / 4 */
45 [ 4] = 1, /* CC2 PPL / 1 */
46 [ 5] = 1, /* CC2 PPL / 2 */
47 [ 6] = 1, /* CC2 PPL / 4 */
48 [ 8] = 2, /* CC3 PPL / 1 */
49 [ 9] = 2, /* CC3 PPL / 2 */
50 [10] = 2, /* CC3 PPL / 4 */
51 [12] = 3, /* CC4 PPL / 1 */
52 [13] = 3, /* CC4 PPL / 2 */
53 [14] = 3, /* CC4 PPL / 4 */
54 };
55
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +053056 const u8 core_cplx_pll_div[16] = {
Kumar Gala39aaca12009-03-19 02:46:19 -050057 [ 0] = 1, /* CC1 PPL / 1 */
58 [ 1] = 2, /* CC1 PPL / 2 */
59 [ 2] = 4, /* CC1 PPL / 4 */
60 [ 4] = 1, /* CC2 PPL / 1 */
61 [ 5] = 2, /* CC2 PPL / 2 */
62 [ 6] = 4, /* CC2 PPL / 4 */
63 [ 8] = 1, /* CC3 PPL / 1 */
64 [ 9] = 2, /* CC3 PPL / 2 */
65 [10] = 4, /* CC3 PPL / 4 */
66 [12] = 1, /* CC4 PPL / 1 */
67 [13] = 2, /* CC4 PPL / 2 */
68 [14] = 4, /* CC4 PPL / 4 */
69 };
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +053070 uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
71#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
72 uint rcw_tmp;
73#endif
74 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
Kumar Gala39aaca12009-03-19 02:46:19 -050075 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +080076 uint mem_pll_rat;
Priyanka Jainb1359912013-12-17 14:25:52 +053077#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
78 uint single_src;
79#endif
Kumar Gala39aaca12009-03-19 02:46:19 -050080
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +053081 sys_info->freq_systembus = sysclk;
Priyanka Jainb1359912013-12-17 14:25:52 +053082#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
83 /*
84 * DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
85 * are driven by separate DDR Refclock or single source
86 * differential clock.
87 */
88 single_src = (in_be32(&gur->rcwsr[5]) >>
89 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
90 FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
91 /*
92 * For single source clocking, both ddrclock and syclock
93 * are driven by differential sysclock.
94 */
95 if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) {
96 printf("Single Source Clock Configuration\n");
97 sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
98 } else
99#endif
York Sun98ffa192012-10-08 07:44:31 +0000100#ifdef CONFIG_DDR_CLK_FREQ
Priyanka Jainb1359912013-12-17 14:25:52 +0530101 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
York Sun98ffa192012-10-08 07:44:31 +0000102#else
Priyanka Jainb1359912013-12-17 14:25:52 +0530103 sys_info->freq_ddrbus = sysclk;
York Sun98ffa192012-10-08 07:44:31 +0000104#endif
Kumar Gala39aaca12009-03-19 02:46:19 -0500105
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530106 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
York Sunf77329c2012-10-08 07:44:09 +0000107 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>
108 FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT)
109 & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
Zang Roy-R61911e88f4212013-11-28 13:23:37 +0800110 /* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
111 * T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
112 * it uses 6.
113 */
114#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
115 if (SVR_MAJ(get_svr()) >= 2)
116 mem_pll_rat *= 2;
117#endif
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800118 if (mem_pll_rat > 2)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530119 sys_info->freq_ddrbus *= mem_pll_rat;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800120 else
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530121 sys_info->freq_ddrbus = sys_info->freq_systembus * mem_pll_rat;
Kumar Gala39aaca12009-03-19 02:46:19 -0500122
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530123 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
124 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0x3f;
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800125 if (ratio[i] > 4)
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530126 freq_c_pll[i] = sysclk * ratio[i];
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800127 else
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530128 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
Srikanth Srinivasanab48ca12010-02-10 17:32:43 +0800129 }
York Sun9a653a92012-10-08 07:44:11 +0000130#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
131 /*
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530132 * As per CHASSIS2 architeture total 12 clusters are posible and
York Sun9a653a92012-10-08 07:44:11 +0000133 * Each cluster has up to 4 cores, sharing the same PLL selection.
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530134 * The cluster clock assignment is SoC defined.
135 *
136 * Total 4 clock groups are possible with 3 PLLs each.
137 * as per array indices, clock group A has 0, 1, 2 numbered PLLs &
138 * clock group B has 3, 4, 6 and so on.
139 *
140 * Clock group A having PLL1, PLL2, PLL3, feeding cores of any cluster
141 * depends upon the SoC architeture. Same applies to other
142 * clock groups and clusters.
143 *
York Sun9a653a92012-10-08 07:44:11 +0000144 */
145 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
York Sunf6981432013-03-25 07:40:07 +0000146 int cluster = fsl_qoriq_core_to_cluster(cpu);
147 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
York Sun9a653a92012-10-08 07:44:11 +0000148 & 0xf;
149 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530150 cplx_pll += cc_group[cluster] - 1;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530151 sys_info->freq_processor[cpu] =
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530152 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
York Sun9a653a92012-10-08 07:44:11 +0000153 }
Shengzhou Liu35c471e2014-01-21 14:11:47 +0800154#if defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_T2080) || \
155 defined(CONFIG_PPC_T2081)
Sandeep Singh0cb33252013-03-25 07:33:09 +0000156#define FM1_CLK_SEL 0xe0000000
157#define FM1_CLK_SHIFT 29
158#else
York Sun9a653a92012-10-08 07:44:11 +0000159#define PME_CLK_SEL 0xe0000000
160#define PME_CLK_SHIFT 29
161#define FM1_CLK_SEL 0x1c000000
162#define FM1_CLK_SHIFT 26
Sandeep Singh0cb33252013-03-25 07:33:09 +0000163#endif
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530164#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
York Sun9a653a92012-10-08 07:44:11 +0000165 rcw_tmp = in_be32(&gur->rcwsr[7]);
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530166#endif
York Sun9a653a92012-10-08 07:44:11 +0000167
168#ifdef CONFIG_SYS_DPAA_PME
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530169#ifndef CONFIG_PME_PLAT_CLK_DIV
York Sun9a653a92012-10-08 07:44:11 +0000170 switch ((rcw_tmp & PME_CLK_SEL) >> PME_CLK_SHIFT) {
171 case 1:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530172 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK];
York Sun9a653a92012-10-08 07:44:11 +0000173 break;
174 case 2:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530175 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000176 break;
177 case 3:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530178 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000179 break;
180 case 4:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530181 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK] / 4;
York Sun9a653a92012-10-08 07:44:11 +0000182 break;
183 case 6:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530184 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000185 break;
186 case 7:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530187 sys_info->freq_pme = freq_c_pll[CONFIG_SYS_PME_CLK + 1] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000188 break;
189 default:
190 printf("Error: Unknown PME clock select!\n");
191 case 0:
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530192 sys_info->freq_pme = sys_info->freq_systembus / 2;
York Sun9a653a92012-10-08 07:44:11 +0000193 break;
194
195 }
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530196#else
197 sys_info->freq_pme = sys_info->freq_systembus / CONFIG_SYS_PME_CLK;
198
199#endif
York Sun9a653a92012-10-08 07:44:11 +0000200#endif
201
Haiying Wang990e1a82012-10-11 07:13:39 +0000202#ifdef CONFIG_SYS_DPAA_QBMAN
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530203 sys_info->freq_qman = sys_info->freq_systembus / 2;
Haiying Wang990e1a82012-10-11 07:13:39 +0000204#endif
205
York Sun9a653a92012-10-08 07:44:11 +0000206#ifdef CONFIG_SYS_DPAA_FMAN
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530207#ifndef CONFIG_FM_PLAT_CLK_DIV
York Sun9a653a92012-10-08 07:44:11 +0000208 switch ((rcw_tmp & FM1_CLK_SEL) >> FM1_CLK_SHIFT) {
209 case 1:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530210 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK];
York Sun9a653a92012-10-08 07:44:11 +0000211 break;
212 case 2:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530213 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000214 break;
215 case 3:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530216 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000217 break;
218 case 4:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530219 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK] / 4;
York Sun9a653a92012-10-08 07:44:11 +0000220 break;
Sandeep Singh0cb33252013-03-25 07:33:09 +0000221 case 5:
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530222 sys_info->freq_fman[0] = sys_info->freq_systembus;
Sandeep Singh0cb33252013-03-25 07:33:09 +0000223 break;
York Sun9a653a92012-10-08 07:44:11 +0000224 case 6:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530225 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000226 break;
227 case 7:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530228 sys_info->freq_fman[0] = freq_c_pll[CONFIG_SYS_FM1_CLK + 1] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000229 break;
230 default:
231 printf("Error: Unknown FMan1 clock select!\n");
232 case 0:
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530233 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
York Sun9a653a92012-10-08 07:44:11 +0000234 break;
235 }
236#if (CONFIG_SYS_NUM_FMAN) == 2
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530237#ifdef CONFIG_SYS_FM2_CLK
York Sun9a653a92012-10-08 07:44:11 +0000238#define FM2_CLK_SEL 0x00000038
239#define FM2_CLK_SHIFT 3
240 rcw_tmp = in_be32(&gur->rcwsr[15]);
241 switch ((rcw_tmp & FM2_CLK_SEL) >> FM2_CLK_SHIFT) {
242 case 1:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530243 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1];
York Sun9a653a92012-10-08 07:44:11 +0000244 break;
245 case 2:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530246 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000247 break;
248 case 3:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530249 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000250 break;
251 case 4:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530252 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK + 1] / 4;
York Sun9a653a92012-10-08 07:44:11 +0000253 break;
Shaohui Xiec1015c62013-11-28 13:52:51 +0800254 case 5:
255 sys_info->freq_fman[1] = sys_info->freq_systembus;
256 break;
York Sun9a653a92012-10-08 07:44:11 +0000257 case 6:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530258 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 2;
York Sun9a653a92012-10-08 07:44:11 +0000259 break;
260 case 7:
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530261 sys_info->freq_fman[1] = freq_c_pll[CONFIG_SYS_FM2_CLK] / 3;
York Sun9a653a92012-10-08 07:44:11 +0000262 break;
263 default:
264 printf("Error: Unknown FMan2 clock select!\n");
265 case 0:
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530266 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
York Sun9a653a92012-10-08 07:44:11 +0000267 break;
268 }
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530269#endif
York Sun9a653a92012-10-08 07:44:11 +0000270#endif /* CONFIG_SYS_NUM_FMAN == 2 */
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530271#else
272 sys_info->freq_fman[0] = sys_info->freq_systembus / CONFIG_SYS_FM1_CLK;
273#endif
274#endif
York Sun9a653a92012-10-08 07:44:11 +0000275
276#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
277
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500278 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
York Sunf6981432013-03-25 07:40:07 +0000279 u32 c_pll_sel = (in_be32(&clk->clkcsr[cpu].clkcncsr) >> 27)
280 & 0xf;
Kumar Gala39aaca12009-03-19 02:46:19 -0500281 u32 cplx_pll = core_cplx_PLL[c_pll_sel];
282
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530283 sys_info->freq_processor[cpu] =
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530284 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
Kumar Gala39aaca12009-03-19 02:46:19 -0500285 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500286#define PME_CLK_SEL 0x80000000
287#define FM1_CLK_SEL 0x40000000
288#define FM2_CLK_SEL 0x20000000
Kumar Galab5c87532011-02-16 02:03:29 -0600289#define HWA_ASYNC_DIV 0x04000000
290#if (CONFIG_SYS_FSL_NUM_CC_PLLS == 2)
291#define HWA_CC_PLL 1
Timur Tabi49054432012-10-05 11:09:19 +0000292#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 3)
293#define HWA_CC_PLL 2
Kumar Galab5c87532011-02-16 02:03:29 -0600294#elif (CONFIG_SYS_FSL_NUM_CC_PLLS == 4)
Wolfgang Denkcd6881b2011-05-19 22:21:41 +0200295#define HWA_CC_PLL 2
Kumar Galab5c87532011-02-16 02:03:29 -0600296#else
297#error CONFIG_SYS_FSL_NUM_CC_PLLS not set or unknown case
298#endif
Kumar Gala39aaca12009-03-19 02:46:19 -0500299 rcw_tmp = in_be32(&gur->rcwsr[7]);
300
301#ifdef CONFIG_SYS_DPAA_PME
Kumar Galab5c87532011-02-16 02:03:29 -0600302 if (rcw_tmp & PME_CLK_SEL) {
303 if (rcw_tmp & HWA_ASYNC_DIV)
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530304 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 4;
Kumar Galab5c87532011-02-16 02:03:29 -0600305 else
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530306 sys_info->freq_pme = freq_c_pll[HWA_CC_PLL] / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600307 } else {
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530308 sys_info->freq_pme = sys_info->freq_systembus / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600309 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500310#endif
311
312#ifdef CONFIG_SYS_DPAA_FMAN
Kumar Galab5c87532011-02-16 02:03:29 -0600313 if (rcw_tmp & FM1_CLK_SEL) {
314 if (rcw_tmp & HWA_ASYNC_DIV)
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530315 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 4;
Kumar Galab5c87532011-02-16 02:03:29 -0600316 else
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530317 sys_info->freq_fman[0] = freq_c_pll[HWA_CC_PLL] / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600318 } else {
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530319 sys_info->freq_fman[0] = sys_info->freq_systembus / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600320 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500321#if (CONFIG_SYS_NUM_FMAN) == 2
Kumar Galab5c87532011-02-16 02:03:29 -0600322 if (rcw_tmp & FM2_CLK_SEL) {
323 if (rcw_tmp & HWA_ASYNC_DIV)
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530324 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 4;
Kumar Galab5c87532011-02-16 02:03:29 -0600325 else
Prabhakar Kushwahace746fe2013-09-03 11:20:15 +0530326 sys_info->freq_fman[1] = freq_c_pll[HWA_CC_PLL] / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600327 } else {
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530328 sys_info->freq_fman[1] = sys_info->freq_systembus / 2;
Kumar Galab5c87532011-02-16 02:03:29 -0600329 }
Kumar Gala39aaca12009-03-19 02:46:19 -0500330#endif
331#endif
332
Shaohui Xie3e83fc92013-03-25 07:33:25 +0000333#ifdef CONFIG_SYS_DPAA_QBMAN
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530334 sys_info->freq_qman = sys_info->freq_systembus / 2;
Shaohui Xie3e83fc92013-03-25 07:33:25 +0000335#endif
336
York Sun9a653a92012-10-08 07:44:11 +0000337#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
338
339#else /* CONFIG_FSL_CORENET */
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530340 uint plat_ratio, e500_ratio, half_freq_systembus;
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500341 int i;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400342#ifdef CONFIG_QE
Haiying Wanga52d2f82011-02-11 01:25:30 -0600343 __maybe_unused u32 qe_ratio;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400344#endif
wdenk42d1f032003-10-15 23:53:47 +0000345
346 plat_ratio = (gur->porpllsr) & 0x0000003e;
347 plat_ratio >>= 1;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530348 sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ;
Andy Fleming66ed6cc2007-04-23 02:37:47 -0500349
350 /* Divide before multiply to avoid integer
351 * overflow for processor speeds above 2GHz */
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530352 half_freq_systembus = sys_info->freq_systembus/2;
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530353 for (i = 0; i < cpu_numcores(); i++) {
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500354 e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530355 sys_info->freq_processor[i] = e500_ratio * half_freq_systembus;
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500356 }
James Yanga3e77fa2008-02-08 18:05:08 -0600357
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530358 /* Note: freq_ddrbus is the MCLK frequency, not the data rate. */
359 sys_info->freq_ddrbus = sys_info->freq_systembus;
Kumar Galad4357932007-12-07 04:59:26 -0600360
361#ifdef CONFIG_DDR_CLK_FREQ
362 {
Jason Jinc0391112008-09-27 14:40:57 +0800363 u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
364 >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
Kumar Galad4357932007-12-07 04:59:26 -0600365 if (ddr_ratio != 0x7)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530366 sys_info->freq_ddrbus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
Kumar Galad4357932007-12-07 04:59:26 -0600367 }
368#endif
Trent Piephoada591d2008-12-03 15:16:37 -0800369
Haiying Wangb3d7f202009-05-20 12:30:29 -0400370#ifdef CONFIG_QE
York Sunbe7bebe2012-08-10 11:07:26 +0000371#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530372 sys_info->freq_qe = sys_info->freq_systembus;
Haiying Wanga52d2f82011-02-11 01:25:30 -0600373#else
Haiying Wangb3d7f202009-05-20 12:30:29 -0400374 qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
375 >> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530376 sys_info->freq_qe = qe_ratio * CONFIG_SYS_CLK_FREQ;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400377#endif
Haiying Wanga52d2f82011-02-11 01:25:30 -0600378#endif
Haiying Wangb3d7f202009-05-20 12:30:29 -0400379
Haiying Wang24995d82011-01-20 22:26:31 +0000380#ifdef CONFIG_SYS_DPAA_FMAN
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530381 sys_info->freq_fman[0] = sys_info->freq_systembus;
Haiying Wang24995d82011-01-20 22:26:31 +0000382#endif
383
384#endif /* CONFIG_FSL_CORENET */
385
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530386#if defined(CONFIG_FSL_LBC)
York Sun9a653a92012-10-08 07:44:11 +0000387 uint lcrr_div;
Trent Piephoada591d2008-12-03 15:16:37 -0800388#if defined(CONFIG_SYS_LBC_LCRR)
389 /* We will program LCRR to this value later */
390 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
391#else
Becky Brucef51cdaf2010-06-17 11:37:20 -0500392 lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
Trent Piephoada591d2008-12-03 15:16:37 -0800393#endif
394 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
Dave Liu0fd2fa62009-11-17 20:49:05 +0800395#if defined(CONFIG_FSL_CORENET)
396 /* If this is corenet based SoC, bit-representation
397 * for four times the clock divider values.
398 */
399 lcrr_div *= 4;
400#elif !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
Trent Piephoada591d2008-12-03 15:16:37 -0800401 !defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
402 /*
403 * Yes, the entire PQ38 family use the same
404 * bit-representation for twice the clock divider values.
405 */
406 lcrr_div *= 2;
407#endif
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530408 sys_info->freq_localbus = sys_info->freq_systembus / lcrr_div;
Trent Piephoada591d2008-12-03 15:16:37 -0800409 } else {
410 /* In case anyone cares what the unknown value is */
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530411 sys_info->freq_localbus = lcrr_div;
Trent Piephoada591d2008-12-03 15:16:37 -0800412 }
Dipen Dudhatbeba93e2011-01-19 12:46:27 +0530413#endif
Kumar Gala800c73c2012-10-08 07:44:06 +0000414
415#if defined(CONFIG_FSL_IFC)
416 ccr = in_be32(&ifc_regs->ifc_ccr);
417 ccr = ((ccr & IFC_CCR_CLK_DIV_MASK) >> IFC_CCR_CLK_DIV_SHIFT) + 1;
418
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530419 sys_info->freq_localbus = sys_info->freq_systembus / ccr;
Kumar Gala800c73c2012-10-08 07:44:06 +0000420#endif
wdenk42d1f032003-10-15 23:53:47 +0000421}
422
Andy Fleming66ed6cc2007-04-23 02:37:47 -0500423
wdenk42d1f032003-10-15 23:53:47 +0000424int get_clocks (void)
425{
wdenk42d1f032003-10-15 23:53:47 +0000426 sys_info_t sys_info;
Timur Tabi88353a92008-04-04 11:15:58 -0500427#ifdef CONFIG_MPC8544
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428 volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
Timur Tabi88353a92008-04-04 11:15:58 -0500429#endif
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500430#if defined(CONFIG_CPM2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
wdenk42d1f032003-10-15 23:53:47 +0000432 uint sccr, dfbrg;
433
434 /* set VCO = 4 * BRG */
Kumar Galaaafeefb2007-11-28 00:36:33 -0600435 cpm->im_cpm_intctl.sccr &= 0xfffffffc;
436 sccr = cpm->im_cpm_intctl.sccr;
wdenk42d1f032003-10-15 23:53:47 +0000437 dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
438#endif
439 get_sys_info (&sys_info);
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530440 gd->cpu_clk = sys_info.freq_processor[0];
441 gd->bus_clk = sys_info.freq_systembus;
442 gd->mem_clk = sys_info.freq_ddrbus;
443 gd->arch.lbc_clk = sys_info.freq_localbus;
Timur Tabi88353a92008-04-04 11:15:58 -0500444
Haiying Wangb3d7f202009-05-20 12:30:29 -0400445#ifdef CONFIG_QE
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530446 gd->arch.qe_clk = sys_info.freq_qe;
Simon Glass45bae2e2012-12-13 20:48:50 +0000447 gd->arch.brg_clk = gd->arch.qe_clk / 2;
Haiying Wangb3d7f202009-05-20 12:30:29 -0400448#endif
Timur Tabi88353a92008-04-04 11:15:58 -0500449 /*
450 * The base clock for I2C depends on the actual SOC. Unfortunately,
451 * there is no pattern that can be used to determine the frequency, so
452 * the only choice is to look up the actual SOC number and use the value
453 * for that SOC. This information is taken from application note
454 * AN2919.
455 */
456#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
Tang Yuantianf62b1232013-09-06 10:45:40 +0800457 defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555) || \
458 defined(CONFIG_P1022)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530459 gd->arch.i2c1_clk = sys_info.freq_systembus;
Timur Tabi88353a92008-04-04 11:15:58 -0500460#elif defined(CONFIG_MPC8544)
461 /*
462 * On the 8544, the I2C clock is the same as the SEC clock. This can be
463 * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
464 * 4.4.3.3 of the 8544 RM. Note that this might actually work for all
465 * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
466 * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
467 */
468 if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530469 gd->arch.i2c1_clk = sys_info.freq_systembus / 3;
Kumar Gala42653b82008-10-16 21:58:49 -0500470 else
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530471 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
Timur Tabi88353a92008-04-04 11:15:58 -0500472#else
473 /* Most 85xx SOCs use CCB/2, so this is the default behavior. */
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530474 gd->arch.i2c1_clk = sys_info.freq_systembus / 2;
Timur Tabi88353a92008-04-04 11:15:58 -0500475#endif
Simon Glass609e6ec2012-12-13 20:48:49 +0000476 gd->arch.i2c2_clk = gd->arch.i2c1_clk;
Timur Tabi943afa22008-01-09 14:35:26 -0600477
Dipen Dudhat6b9ea082009-09-01 17:27:00 +0530478#if defined(CONFIG_FSL_ESDHC)
Priyanka Jain7d640e92011-02-08 15:45:25 +0530479#if defined(CONFIG_MPC8569) || defined(CONFIG_P1010) ||\
480 defined(CONFIG_P1014)
Simon Glasse9adeca2012-12-13 20:49:05 +0000481 gd->arch.sdhc_clk = gd->bus_clk;
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400482#else
Simon Glasse9adeca2012-12-13 20:49:05 +0000483 gd->arch.sdhc_clk = gd->bus_clk / 2;
Kumar Galaef50d6c2008-08-12 11:14:19 -0500484#endif
Anton Vorontsov7f52ed52009-10-15 17:47:06 +0400485#endif /* defined(CONFIG_FSL_ESDHC) */
Kumar Galaef50d6c2008-08-12 11:14:19 -0500486
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500487#if defined(CONFIG_CPM2)
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530488 gd->arch.vco_out = 2*sys_info.freq_systembus;
Simon Glass748cd052012-12-13 20:48:46 +0000489 gd->arch.cpm_clk = gd->arch.vco_out / 2;
490 gd->arch.scc_clk = gd->arch.vco_out / 4;
491 gd->arch.brg_clk = gd->arch.vco_out / (1 << (2 * (dfbrg + 1)));
wdenk42d1f032003-10-15 23:53:47 +0000492#endif
493
494 if(gd->cpu_clk != 0) return (0);
495 else return (1);
496}
497
498
499/********************************************
500 * get_bus_freq
501 * return system bus freq in Hz
502 *********************************************/
503ulong get_bus_freq (ulong dummy)
504{
James Yanga3e77fa2008-02-08 18:05:08 -0600505 return gd->bus_clk;
wdenk42d1f032003-10-15 23:53:47 +0000506}
Kumar Galad4357932007-12-07 04:59:26 -0600507
508/********************************************
509 * get_ddr_freq
510 * return ddr bus freq in Hz
511 *********************************************/
512ulong get_ddr_freq (ulong dummy)
513{
James Yanga3e77fa2008-02-08 18:05:08 -0600514 return gd->mem_clk;
Kumar Galad4357932007-12-07 04:59:26 -0600515}