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Mike Frysingerbe853bf2008-10-06 04:16:47 -04001/*
Scott Jiangfea9b692014-11-13 15:30:53 +08002 * i2c.c - driver for ADI TWI/I2C
Mike Frysingerbe853bf2008-10-06 04:16:47 -04003 *
Scott Jiangfea9b692014-11-13 15:30:53 +08004 * Copyright (c) 2006-2014 Analog Devices Inc.
Mike Frysingerbe853bf2008-10-06 04:16:47 -04005 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <common.h>
10#include <i2c.h>
11
Sonic Zhangd6a320d2014-01-28 13:53:34 +080012#include <asm/clock.h>
Scott Jiangfea9b692014-11-13 15:30:53 +080013#include <asm/twi.h>
Scott Jianga6be70f2014-11-13 15:30:54 +080014#include <asm/io.h>
Mike Frysingerbe853bf2008-10-06 04:16:47 -040015
Scott Jiangc4697032014-11-13 15:30:55 +080016static struct twi_regs *i2c_get_base(struct i2c_adapter *adap);
17
Mike Frysingerb5cebb42010-05-05 03:20:30 -040018/* Every register is 32bit aligned, but only 16bits in size */
19#define ureg(name) u16 name; u16 __pad_##name;
20struct twi_regs {
21 ureg(clkdiv);
22 ureg(control);
23 ureg(slave_ctl);
24 ureg(slave_stat);
25 ureg(slave_addr);
26 ureg(master_ctl);
27 ureg(master_stat);
28 ureg(master_addr);
29 ureg(int_stat);
30 ureg(int_mask);
31 ureg(fifo_ctl);
32 ureg(fifo_stat);
33 char __pad[0x50];
34 ureg(xmt_data8);
35 ureg(xmt_data16);
36 ureg(rcv_data8);
37 ureg(rcv_data16);
38};
39#undef ureg
40
Mike Frysingerb5cebb42010-05-05 03:20:30 -040041#ifdef TWI_CLKDIV
42#define TWI0_CLKDIV TWI_CLKDIV
Scott Jiangc4697032014-11-13 15:30:55 +080043# ifdef CONFIG_SYS_MAX_I2C_BUS
44# undef CONFIG_SYS_MAX_I2C_BUS
45# endif
46#define CONFIG_SYS_MAX_I2C_BUS 1
Mike Frysingerbe853bf2008-10-06 04:16:47 -040047#endif
Mike Frysinger08a1c622009-10-14 19:27:27 -040048
49/*
50 * The way speed is changed into duty often results in integer truncation
51 * with 50% duty, so we'll force rounding up to the next duty by adding 1
52 * to the max. In practice this will get us a speed of something like
53 * 385 KHz. The other limit is easy to handle as it is only 8 bits.
54 */
55#define I2C_SPEED_MAX 400000
56#define I2C_SPEED_TO_DUTY(speed) (5000000 / (speed))
57#define I2C_DUTY_MAX (I2C_SPEED_TO_DUTY(I2C_SPEED_MAX) + 1)
58#define I2C_DUTY_MIN 0xff /* 8 bit limited */
59#define SYS_I2C_DUTY I2C_SPEED_TO_DUTY(CONFIG_SYS_I2C_SPEED)
60/* Note: duty is inverse of speed, so the comparisons below are correct */
61#if SYS_I2C_DUTY < I2C_DUTY_MAX || SYS_I2C_DUTY > I2C_DUTY_MIN
Scott Jiangc4697032014-11-13 15:30:55 +080062# error "The I2C hardware can only operate 20KHz - 400KHz"
Mike Frysingerbe853bf2008-10-06 04:16:47 -040063#endif
64
65/* All transfers are described by this data structure */
66struct i2c_msg {
67 u8 flags;
68#define I2C_M_COMBO 0x4
69#define I2C_M_STOP 0x2
70#define I2C_M_READ 0x1
71 int len; /* msg length */
72 u8 *buf; /* pointer to msg data */
73 int alen; /* addr length */
74 u8 *abuf; /* addr buffer */
75};
76
Mike Frysinger3814ea42009-10-14 19:27:26 -040077/* Allow msec timeout per ~byte transfer */
78#define I2C_TIMEOUT 10
79
Mike Frysingerbe853bf2008-10-06 04:16:47 -040080/**
81 * wait_for_completion - manage the actual i2c transfer
82 * @msg: the i2c msg
83 */
Scott Jiangc4697032014-11-13 15:30:55 +080084static int wait_for_completion(struct twi_regs *twi, struct i2c_msg *msg)
Mike Frysingerbe853bf2008-10-06 04:16:47 -040085{
Scott Jianga6be70f2014-11-13 15:30:54 +080086 u16 int_stat, ctl;
Mike Frysinger3814ea42009-10-14 19:27:26 -040087 ulong timebase = get_timer(0);
Mike Frysingerbe853bf2008-10-06 04:16:47 -040088
Mike Frysinger3814ea42009-10-14 19:27:26 -040089 do {
Scott Jianga6be70f2014-11-13 15:30:54 +080090 int_stat = readw(&twi->int_stat);
Mike Frysingerbe853bf2008-10-06 04:16:47 -040091
92 if (int_stat & XMTSERV) {
Scott Jianga6be70f2014-11-13 15:30:54 +080093 writew(XMTSERV, &twi->int_stat);
Mike Frysingerbe853bf2008-10-06 04:16:47 -040094 if (msg->alen) {
Scott Jianga6be70f2014-11-13 15:30:54 +080095 writew(*(msg->abuf++), &twi->xmt_data8);
Mike Frysingerbe853bf2008-10-06 04:16:47 -040096 --msg->alen;
97 } else if (!(msg->flags & I2C_M_COMBO) && msg->len) {
Scott Jianga6be70f2014-11-13 15:30:54 +080098 writew(*(msg->buf++), &twi->xmt_data8);
Mike Frysingerbe853bf2008-10-06 04:16:47 -040099 --msg->len;
100 } else {
Scott Jianga6be70f2014-11-13 15:30:54 +0800101 ctl = readw(&twi->master_ctl);
102 if (msg->flags & I2C_M_COMBO)
103 writew(ctl | RSTART | MDIR,
104 &twi->master_ctl);
105 else
106 writew(ctl | STOP, &twi->master_ctl);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400107 }
108 }
109 if (int_stat & RCVSERV) {
Scott Jianga6be70f2014-11-13 15:30:54 +0800110 writew(RCVSERV, &twi->int_stat);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400111 if (msg->len) {
Scott Jianga6be70f2014-11-13 15:30:54 +0800112 *(msg->buf++) = readw(&twi->rcv_data8);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400113 --msg->len;
114 } else if (msg->flags & I2C_M_STOP) {
Scott Jianga6be70f2014-11-13 15:30:54 +0800115 ctl = readw(&twi->master_ctl);
116 writew(ctl | STOP, &twi->master_ctl);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400117 }
118 }
119 if (int_stat & MERR) {
Scott Jianga6be70f2014-11-13 15:30:54 +0800120 writew(MERR, &twi->int_stat);
Mike Frysinger3814ea42009-10-14 19:27:26 -0400121 return msg->len;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400122 }
123 if (int_stat & MCOMP) {
Scott Jianga6be70f2014-11-13 15:30:54 +0800124 writew(MCOMP, &twi->int_stat);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400125 if (msg->flags & I2C_M_COMBO && msg->len) {
Scott Jianga6be70f2014-11-13 15:30:54 +0800126 ctl = readw(&twi->master_ctl);
127 ctl = (ctl & ~RSTART) |
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400128 (min(msg->len, 0xff) << 6) | MEN | MDIR;
Scott Jianga6be70f2014-11-13 15:30:54 +0800129 writew(ctl, &twi->master_ctl);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400130 } else
131 break;
132 }
Mike Frysinger3814ea42009-10-14 19:27:26 -0400133
134 /* If we were able to do something, reset timeout */
135 if (int_stat)
136 timebase = get_timer(0);
137
138 } while (get_timer(timebase) < I2C_TIMEOUT);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400139
140 return msg->len;
141}
142
Scott Jiangc4697032014-11-13 15:30:55 +0800143static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr,
144 int alen, uint8_t *buffer, int len, uint8_t flags)
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400145{
Scott Jiangc4697032014-11-13 15:30:55 +0800146 struct twi_regs *twi = i2c_get_base(adap);
Scott Jianga6be70f2014-11-13 15:30:54 +0800147 int ret;
148 u16 ctl;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400149 uchar addr_buffer[] = {
150 (addr >> 0),
151 (addr >> 8),
152 (addr >> 16),
153 };
154 struct i2c_msg msg = {
155 .flags = flags | (len >= 0xff ? I2C_M_STOP : 0),
156 .buf = buffer,
157 .len = len,
158 .abuf = addr_buffer,
159 .alen = alen,
160 };
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400161
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400162 /* wait for things to settle */
Scott Jianga6be70f2014-11-13 15:30:54 +0800163 while (readw(&twi->master_stat) & BUSBUSY)
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400164 if (ctrlc())
165 return 1;
166
167 /* Set Transmit device address */
Scott Jianga6be70f2014-11-13 15:30:54 +0800168 writew(chip, &twi->master_addr);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400169
170 /* Clear the FIFO before starting things */
Scott Jianga6be70f2014-11-13 15:30:54 +0800171 writew(XMTFLUSH | RCVFLUSH, &twi->fifo_ctl);
172 writew(0, &twi->fifo_ctl);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400173
174 /* prime the pump */
175 if (msg.alen) {
Peter Meerwald98ab14e2009-06-29 15:48:33 -0400176 len = (msg.flags & I2C_M_COMBO) ? msg.alen : msg.alen + len;
Scott Jianga6be70f2014-11-13 15:30:54 +0800177 writew(*(msg.abuf++), &twi->xmt_data8);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400178 --msg.alen;
179 } else if (!(msg.flags & I2C_M_READ) && msg.len) {
Scott Jianga6be70f2014-11-13 15:30:54 +0800180 writew(*(msg.buf++), &twi->xmt_data8);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400181 --msg.len;
182 }
183
184 /* clear int stat */
Scott Jianga6be70f2014-11-13 15:30:54 +0800185 writew(-1, &twi->master_stat);
186 writew(-1, &twi->int_stat);
187 writew(0, &twi->int_mask);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400188
189 /* Master enable */
Scott Jianga6be70f2014-11-13 15:30:54 +0800190 ctl = readw(&twi->master_ctl);
191 ctl = (ctl & FAST) | (min(len, 0xff) << 6) | MEN |
192 ((msg.flags & I2C_M_READ) ? MDIR : 0);
193 writew(ctl, &twi->master_ctl);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400194
195 /* process the rest */
Scott Jiangc4697032014-11-13 15:30:55 +0800196 ret = wait_for_completion(twi, &msg);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400197
198 if (ret) {
Scott Jianga6be70f2014-11-13 15:30:54 +0800199 ctl = readw(&twi->master_ctl) & ~MEN;
200 writew(ctl, &twi->master_ctl);
201 ctl = readw(&twi->control) & ~TWI_ENA;
202 writew(ctl, &twi->control);
203 ctl = readw(&twi->control) | TWI_ENA;
204 writew(ctl, &twi->control);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400205 }
206
207 return ret;
208}
209
Scott Jiangc4697032014-11-13 15:30:55 +0800210static uint adi_i2c_setspeed(struct i2c_adapter *adap, uint speed)
Mike Frysinger08a1c622009-10-14 19:27:27 -0400211{
Scott Jiangc4697032014-11-13 15:30:55 +0800212 struct twi_regs *twi = i2c_get_base(adap);
Mike Frysinger08a1c622009-10-14 19:27:27 -0400213 u16 clkdiv = I2C_SPEED_TO_DUTY(speed);
214
215 /* Set TWI interface clock */
216 if (clkdiv < I2C_DUTY_MAX || clkdiv > I2C_DUTY_MIN)
217 return -1;
Scott Jianga6be70f2014-11-13 15:30:54 +0800218 clkdiv = (clkdiv << 8) | (clkdiv & 0xff);
219 writew(clkdiv, &twi->clkdiv);
Mike Frysinger08a1c622009-10-14 19:27:27 -0400220
221 /* Don't turn it on */
Scott Jianga6be70f2014-11-13 15:30:54 +0800222 writew(speed > 100000 ? FAST : 0, &twi->master_ctl);
Mike Frysinger08a1c622009-10-14 19:27:27 -0400223
224 return 0;
225}
226
Scott Jiangc4697032014-11-13 15:30:55 +0800227static void adi_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
Mike Frysinger08a1c622009-10-14 19:27:27 -0400228{
Scott Jiangc4697032014-11-13 15:30:55 +0800229 struct twi_regs *twi = i2c_get_base(adap);
230 u16 prescale = ((get_i2c_clk() / 1000 / 1000 + 5) / 10) & 0x7F;
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400231
232 /* Set TWI internal clock as 10MHz */
Scott Jianga6be70f2014-11-13 15:30:54 +0800233 writew(prescale, &twi->control);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400234
235 /* Set TWI interface clock as specified */
Mike Frysinger08a1c622009-10-14 19:27:27 -0400236 i2c_set_bus_speed(speed);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400237
Mike Frysinger08a1c622009-10-14 19:27:27 -0400238 /* Enable it */
Scott Jianga6be70f2014-11-13 15:30:54 +0800239 writew(TWI_ENA | prescale, &twi->control);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400240}
241
Scott Jiangc4697032014-11-13 15:30:55 +0800242static int adi_i2c_read(struct i2c_adapter *adap, uint8_t chip,
243 uint addr, int alen, uint8_t *buffer, int len)
244{
245 return i2c_transfer(adap, chip, addr, alen, buffer,
246 len, alen ? I2C_M_COMBO : I2C_M_READ);
247}
248
249static int adi_i2c_write(struct i2c_adapter *adap, uint8_t chip,
250 uint addr, int alen, uint8_t *buffer, int len)
251{
252 return i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
253}
254
255static int adi_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400256{
257 u8 byte;
Scott Jiangc4697032014-11-13 15:30:55 +0800258 return adi_i2c_read(adap, chip, 0, 0, &byte, 1);
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400259}
260
Scott Jiangc4697032014-11-13 15:30:55 +0800261static struct twi_regs *i2c_get_base(struct i2c_adapter *adap)
Mike Frysingerbe853bf2008-10-06 04:16:47 -0400262{
Scott Jiangc4697032014-11-13 15:30:55 +0800263 switch (adap->hwadapnr) {
264#if CONFIG_SYS_MAX_I2C_BUS > 2
265 case 2:
266 return (struct twi_regs *)TWI2_CLKDIV;
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400267#endif
268#if CONFIG_SYS_MAX_I2C_BUS > 1
Scott Jianga6be70f2014-11-13 15:30:54 +0800269 case 1:
Scott Jiangc4697032014-11-13 15:30:55 +0800270 return (struct twi_regs *)TWI1_CLKDIV;
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400271#endif
Scott Jiangc4697032014-11-13 15:30:55 +0800272 case 0:
273 return (struct twi_regs *)TWI0_CLKDIV;
274
275 default:
276 printf("wrong hwadapnr: %d\n", adap->hwadapnr);
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400277 }
Scott Jiangc4697032014-11-13 15:30:55 +0800278
279 return NULL;
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400280}
281
Scott Jiangc4697032014-11-13 15:30:55 +0800282U_BOOT_I2C_ADAP_COMPLETE(adi_i2c0, adi_i2c_init, adi_i2c_probe,
283 adi_i2c_read, adi_i2c_write,
284 adi_i2c_setspeed,
285 CONFIG_SYS_I2C_SPEED,
286 0,
287 0)
288
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400289#if CONFIG_SYS_MAX_I2C_BUS > 1
Scott Jiangc4697032014-11-13 15:30:55 +0800290U_BOOT_I2C_ADAP_COMPLETE(adi_i2c1, adi_i2c_init, adi_i2c_probe,
291 adi_i2c_read, adi_i2c_write,
292 adi_i2c_setspeed,
293 CONFIG_SYS_I2C_SPEED,
294 0,
295 1)
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400296#endif
Scott Jiangc4697032014-11-13 15:30:55 +0800297
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400298#if CONFIG_SYS_MAX_I2C_BUS > 2
Scott Jiangc4697032014-11-13 15:30:55 +0800299U_BOOT_I2C_ADAP_COMPLETE(adi_i2c2, adi_i2c_init, adi_i2c_probe,
300 adi_i2c_read, adi_i2c_write,
301 adi_i2c_setspeed,
302 CONFIG_SYS_I2C_SPEED,
303 0,
304 2)
Mike Frysingerb5cebb42010-05-05 03:20:30 -0400305#endif