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Quentin Schulz8a4791f2018-08-31 16:28:29 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2012
4 * Armando Visconti, ST Microelectronics, armando.visconti@st.com.
5 *
6 * (C) Copyright 2018
7 * Quentin Schulz, Bootlin, quentin.schulz@bootlin.com
8 *
9 * Driver for ARM PL022 SPI Controller.
10 */
11
Quentin Schulz8a4791f2018-08-31 16:28:29 +020012#include <clk.h>
13#include <common.h>
14#include <dm.h>
Jagan Teki3ae60302018-11-22 11:54:08 +053015#include <dm/platform_data/spi_pl022.h>
Quentin Schulz8a4791f2018-08-31 16:28:29 +020016#include <linux/io.h>
Simon Glass401d1c42020-10-30 21:38:53 -060017#include <asm/global_data.h>
Quentin Schulz8a4791f2018-08-31 16:28:29 +020018#include <spi.h>
19
20#define SSP_CR0 0x000
21#define SSP_CR1 0x004
22#define SSP_DR 0x008
23#define SSP_SR 0x00C
24#define SSP_CPSR 0x010
25#define SSP_IMSC 0x014
26#define SSP_RIS 0x018
27#define SSP_MIS 0x01C
28#define SSP_ICR 0x020
29#define SSP_DMACR 0x024
30#define SSP_CSR 0x030 /* vendor extension */
31#define SSP_ITCR 0x080
32#define SSP_ITIP 0x084
33#define SSP_ITOP 0x088
34#define SSP_TDR 0x08C
35
36#define SSP_PID0 0xFE0
37#define SSP_PID1 0xFE4
38#define SSP_PID2 0xFE8
39#define SSP_PID3 0xFEC
40
41#define SSP_CID0 0xFF0
42#define SSP_CID1 0xFF4
43#define SSP_CID2 0xFF8
44#define SSP_CID3 0xFFC
45
46/* SSP Control Register 0 - SSP_CR0 */
47#define SSP_CR0_SPO (0x1 << 6)
48#define SSP_CR0_SPH (0x1 << 7)
49#define SSP_CR0_BIT_MODE(x) ((x) - 1)
50#define SSP_SCR_MIN (0x00)
51#define SSP_SCR_MAX (0xFF)
52#define SSP_SCR_SHFT 8
53#define DFLT_CLKRATE 2
54
55/* SSP Control Register 1 - SSP_CR1 */
56#define SSP_CR1_MASK_SSE (0x1 << 1)
57
58#define SSP_CPSR_MIN (0x02)
59#define SSP_CPSR_MAX (0xFE)
60#define DFLT_PRESCALE (0x40)
61
62/* SSP Status Register - SSP_SR */
63#define SSP_SR_MASK_TFE (0x1 << 0) /* Transmit FIFO empty */
64#define SSP_SR_MASK_TNF (0x1 << 1) /* Transmit FIFO not full */
65#define SSP_SR_MASK_RNE (0x1 << 2) /* Receive FIFO not empty */
66#define SSP_SR_MASK_RFF (0x1 << 3) /* Receive FIFO full */
67#define SSP_SR_MASK_BSY (0x1 << 4) /* Busy Flag */
68
69struct pl022_spi_slave {
70 void *base;
Quentin Schulz8a4791f2018-08-31 16:28:29 +020071 unsigned int freq;
Quentin Schulz8a4791f2018-08-31 16:28:29 +020072};
73
74/*
75 * ARM PL022 exists in different 'flavors'.
76 * This drivers currently support the standard variant (0x00041022), that has a
77 * 16bit wide and 8 locations deep TX/RX FIFO.
78 */
79static int pl022_is_supported(struct pl022_spi_slave *ps)
80{
81 /* PL022 version is 0x00041022 */
82 if ((readw(ps->base + SSP_PID0) == 0x22) &&
83 (readw(ps->base + SSP_PID1) == 0x10) &&
84 ((readw(ps->base + SSP_PID2) & 0xf) == 0x04) &&
85 (readw(ps->base + SSP_PID3) == 0x00))
86 return 1;
87
88 return 0;
89}
90
Quentin Schulz8a4791f2018-08-31 16:28:29 +020091static int pl022_spi_probe(struct udevice *bus)
92{
Simon Glassc69cda22020-12-03 16:55:20 -070093 struct pl022_spi_pdata *plat = dev_get_plat(bus);
Quentin Schulz8a4791f2018-08-31 16:28:29 +020094 struct pl022_spi_slave *ps = dev_get_priv(bus);
95
96 ps->base = ioremap(plat->addr, plat->size);
Quentin Schulz8a4791f2018-08-31 16:28:29 +020097 ps->freq = plat->freq;
Quentin Schulz8a4791f2018-08-31 16:28:29 +020098
99 /* Check the PL022 version */
100 if (!pl022_is_supported(ps))
101 return -ENOTSUPP;
102
103 /* 8 bits per word, high polarity and default clock rate */
104 writew(SSP_CR0_BIT_MODE(8), ps->base + SSP_CR0);
105 writew(DFLT_PRESCALE, ps->base + SSP_CPSR);
106
107 return 0;
108}
109
110static void flush(struct pl022_spi_slave *ps)
111{
112 do {
113 while (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE)
114 readw(ps->base + SSP_DR);
115 } while (readw(ps->base + SSP_SR) & SSP_SR_MASK_BSY);
116}
117
118static int pl022_spi_claim_bus(struct udevice *dev)
119{
120 struct udevice *bus = dev->parent;
121 struct pl022_spi_slave *ps = dev_get_priv(bus);
122 u16 reg;
123
124 /* Enable the SPI hardware */
125 reg = readw(ps->base + SSP_CR1);
126 reg |= SSP_CR1_MASK_SSE;
127 writew(reg, ps->base + SSP_CR1);
128
129 flush(ps);
130
131 return 0;
132}
133
134static int pl022_spi_release_bus(struct udevice *dev)
135{
136 struct udevice *bus = dev->parent;
137 struct pl022_spi_slave *ps = dev_get_priv(bus);
138 u16 reg;
139
140 flush(ps);
141
142 /* Disable the SPI hardware */
143 reg = readw(ps->base + SSP_CR1);
144 reg &= ~SSP_CR1_MASK_SSE;
145 writew(reg, ps->base + SSP_CR1);
146
147 return 0;
148}
149
150static int pl022_spi_xfer(struct udevice *dev, unsigned int bitlen,
151 const void *dout, void *din, unsigned long flags)
152{
153 struct udevice *bus = dev->parent;
154 struct pl022_spi_slave *ps = dev_get_priv(bus);
155 u32 len_tx = 0, len_rx = 0, len;
156 u32 ret = 0;
157 const u8 *txp = dout;
158 u8 *rxp = din, value;
159
160 if (bitlen == 0)
161 /* Finish any previously submitted transfers */
162 return 0;
163
164 /*
165 * TODO: The controller can do non-multiple-of-8 bit
166 * transfers, but this driver currently doesn't support it.
167 *
168 * It's also not clear how such transfers are supposed to be
169 * represented as a stream of bytes...this is a limitation of
170 * the current SPI interface.
171 */
172 if (bitlen % 8) {
173 /* Errors always terminate an ongoing transfer */
174 flags |= SPI_XFER_END;
175 return -1;
176 }
177
178 len = bitlen / 8;
179
180 while (len_tx < len) {
181 if (readw(ps->base + SSP_SR) & SSP_SR_MASK_TNF) {
182 value = txp ? *txp++ : 0;
183 writew(value, ps->base + SSP_DR);
184 len_tx++;
185 }
186
187 if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
188 value = readw(ps->base + SSP_DR);
189 if (rxp)
190 *rxp++ = value;
191 len_rx++;
192 }
193 }
194
195 while (len_rx < len_tx) {
196 if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {
197 value = readw(ps->base + SSP_DR);
198 if (rxp)
199 *rxp++ = value;
200 len_rx++;
201 }
202 }
203
204 return ret;
205}
206
207static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
208{
209 return rate / (cpsdvsr * (1 + scr));
210}
211
212static int pl022_spi_set_speed(struct udevice *bus, uint speed)
213{
214 struct pl022_spi_slave *ps = dev_get_priv(bus);
215 u16 scr = SSP_SCR_MIN, cr0 = 0, cpsr = SSP_CPSR_MIN, best_scr = scr,
216 best_cpsr = cpsr;
217 u32 min, max, best_freq = 0, tmp;
Quentin Schulz8a4791f2018-08-31 16:28:29 +0200218 u32 rate = ps->freq;
Quentin Schulz8a4791f2018-08-31 16:28:29 +0200219 bool found = false;
220
221 max = spi_rate(rate, SSP_CPSR_MIN, SSP_SCR_MIN);
222 min = spi_rate(rate, SSP_CPSR_MAX, SSP_SCR_MAX);
223
224 if (speed > max || speed < min) {
225 pr_err("Tried to set speed to %dHz but min=%d and max=%d\n",
226 speed, min, max);
227 return -EINVAL;
228 }
229
230 while (cpsr <= SSP_CPSR_MAX && !found) {
231 while (scr <= SSP_SCR_MAX) {
232 tmp = spi_rate(rate, cpsr, scr);
233
234 if (abs(speed - tmp) < abs(speed - best_freq)) {
235 best_freq = tmp;
236 best_cpsr = cpsr;
237 best_scr = scr;
238
239 if (tmp == speed) {
240 found = true;
241 break;
242 }
243 }
244
245 scr++;
246 }
247 cpsr += 2;
248 scr = SSP_SCR_MIN;
249 }
250
251 writew(best_cpsr, ps->base + SSP_CPSR);
252 cr0 = readw(ps->base + SSP_CR0);
253 writew(cr0 | (best_scr << SSP_SCR_SHFT), ps->base + SSP_CR0);
254
255 return 0;
256}
257
258static int pl022_spi_set_mode(struct udevice *bus, uint mode)
259{
260 struct pl022_spi_slave *ps = dev_get_priv(bus);
261 u16 reg;
262
263 reg = readw(ps->base + SSP_CR0);
264 reg &= ~(SSP_CR0_SPH | SSP_CR0_SPO);
265 if (mode & SPI_CPHA)
266 reg |= SSP_CR0_SPH;
267 if (mode & SPI_CPOL)
268 reg |= SSP_CR0_SPO;
269 writew(reg, ps->base + SSP_CR0);
270
271 return 0;
272}
273
274static int pl022_cs_info(struct udevice *bus, uint cs,
275 struct spi_cs_info *info)
276{
277 return 0;
278}
279
280static const struct dm_spi_ops pl022_spi_ops = {
281 .claim_bus = pl022_spi_claim_bus,
282 .release_bus = pl022_spi_release_bus,
283 .xfer = pl022_spi_xfer,
284 .set_speed = pl022_spi_set_speed,
285 .set_mode = pl022_spi_set_mode,
286 .cs_info = pl022_cs_info,
287};
288
289#if !CONFIG_IS_ENABLED(OF_PLATDATA)
Simon Glassd1998a92020-12-03 16:55:21 -0700290static int pl022_spi_of_to_plat(struct udevice *bus)
Jagan Teki3deb1f72018-11-14 15:28:05 +0530291{
Simon Glass0fd3d912020-12-22 19:30:28 -0700292 struct pl022_spi_pdata *plat = dev_get_plat(bus);
Jagan Teki3deb1f72018-11-14 15:28:05 +0530293 const void *fdt = gd->fdt_blob;
294 int node = dev_of_offset(bus);
295 struct clk clkdev;
296 int ret;
297
298 plat->addr = fdtdec_get_addr_size(fdt, node, "reg", &plat->size);
299
300 ret = clk_get_by_index(bus, 0, &clkdev);
301 if (ret)
302 return ret;
303
304 plat->freq = clk_get_rate(&clkdev);
305
306 return 0;
307}
308
Quentin Schulz8a4791f2018-08-31 16:28:29 +0200309static const struct udevice_id pl022_spi_ids[] = {
310 { .compatible = "arm,pl022-spi" },
311 { }
312};
313#endif
314
315U_BOOT_DRIVER(pl022_spi) = {
316 .name = "pl022_spi",
317 .id = UCLASS_SPI,
318#if !CONFIG_IS_ENABLED(OF_PLATDATA)
319 .of_match = pl022_spi_ids,
Simon Glassd1998a92020-12-03 16:55:21 -0700320 .of_to_plat = pl022_spi_of_to_plat,
Quentin Schulz8a4791f2018-08-31 16:28:29 +0200321#endif
Jagan Teki3deb1f72018-11-14 15:28:05 +0530322 .ops = &pl022_spi_ops,
Simon Glasscaa4daa2020-12-03 16:55:18 -0700323 .plat_auto = sizeof(struct pl022_spi_pdata),
Simon Glass41575d82020-12-03 16:55:17 -0700324 .priv_auto = sizeof(struct pl022_spi_slave),
Quentin Schulz8a4791f2018-08-31 16:28:29 +0200325 .probe = pl022_spi_probe,
326};