blob: 1f7679a240e453cc45d9a7ea1b2f33fccdb2d111 [file] [log] [blame]
Ilko Iliev32949232009-06-12 21:20:39 +02001/*
2 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Ilko Iliev32949232009-06-12 21:20:39 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
6 * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Ilko Iliev32949232009-06-12 21:20:39 +02009 */
10
11#include <common.h>
Alexey Brodkin1ace4022014-02-26 17:47:58 +040012#include <linux/sizes.h>
Asen Dimovf47316a2011-07-26 04:48:41 +000013#include <asm/io.h>
Andreas Bießmannac45bb12013-11-29 12:13:45 +010014#include <asm/gpio.h>
Ilko Iliev32949232009-06-12 21:20:39 +020015#include <asm/arch/at91sam9_smc.h>
16#include <asm/arch/at91_common.h>
17#include <asm/arch/at91_pmc.h>
18#include <asm/arch/at91_rstc.h>
Asen Dimove3150c72010-04-06 16:18:04 +030019#include <asm/arch/at91_matrix.h>
Ilko Iliev32949232009-06-12 21:20:39 +020020#include <asm/arch/clk.h>
Asen Dimovf47316a2011-07-26 04:48:41 +000021#include <asm/arch/gpio.h>
22
Ilko Iliev32949232009-06-12 21:20:39 +020023#include <lcd.h>
24#include <atmel_lcdc.h>
25#include <dataflash.h>
26#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
27#include <net.h>
28#endif
29#include <netdev.h>
30
31DECLARE_GLOBAL_DATA_PTR;
32
33/* ------------------------------------------------------------------------- */
34/*
35 * Miscelaneous platform dependent initialisations
36 */
37
38#ifdef CONFIG_CMD_NAND
39static void pm9261_nand_hw_init(void)
40{
41 unsigned long csa;
Asen Dimovf47316a2011-07-26 04:48:41 +000042 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
43 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
44 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
Ilko Iliev32949232009-06-12 21:20:39 +020045
46 /* Enable CS3 */
Asen Dimove3150c72010-04-06 16:18:04 +030047 csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
48 writel(csa, &matrix->csa);
Ilko Iliev32949232009-06-12 21:20:39 +020049
50 /* Configure SMC CS3 for NAND/SmartMedia */
Asen Dimove3150c72010-04-06 16:18:04 +030051 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
52 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
53 &smc->cs[3].setup);
54
55 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
56 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
57 &smc->cs[3].pulse);
58
59 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
60 &smc->cs[3].cycle);
61
62 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
63 AT91_SMC_MODE_EXNW_DISABLE |
Ilko Iliev32949232009-06-12 21:20:39 +020064#ifdef CONFIG_SYS_NAND_DBW_16
Asen Dimove3150c72010-04-06 16:18:04 +030065 AT91_SMC_MODE_DBW_16 |
Ilko Iliev32949232009-06-12 21:20:39 +020066#else /* CONFIG_SYS_NAND_DBW_8 */
Asen Dimove3150c72010-04-06 16:18:04 +030067 AT91_SMC_MODE_DBW_8 |
Ilko Iliev32949232009-06-12 21:20:39 +020068#endif
Asen Dimove3150c72010-04-06 16:18:04 +030069 AT91_SMC_MODE_TDF_CYCLE(2),
70 &smc->cs[3].mode);
71
Asen Dimovf47316a2011-07-26 04:48:41 +000072 writel(1 << ATMEL_ID_PIOA |
73 1 << ATMEL_ID_PIOC,
Asen Dimove3150c72010-04-06 16:18:04 +030074 &pmc->pcer);
Ilko Iliev32949232009-06-12 21:20:39 +020075
76 /* Configure RDY/BSY */
Andreas Bießmannac45bb12013-11-29 12:13:45 +010077 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
Ilko Iliev32949232009-06-12 21:20:39 +020078
79 /* Enable NandFlash */
Andreas Bießmannac45bb12013-11-29 12:13:45 +010080 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
Ilko Iliev32949232009-06-12 21:20:39 +020081
Asen Dimove3150c72010-04-06 16:18:04 +030082 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
83 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
Ilko Iliev32949232009-06-12 21:20:39 +020084}
85#endif
86
87
88#ifdef CONFIG_DRIVER_DM9000
89static void pm9261_dm9000_hw_init(void)
90{
Asen Dimovf47316a2011-07-26 04:48:41 +000091 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
92 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
Asen Dimove3150c72010-04-06 16:18:04 +030093
Ilko Iliev32949232009-06-12 21:20:39 +020094 /* Configure SMC CS2 for DM9000 */
Asen Dimove3150c72010-04-06 16:18:04 +030095 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
96 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
97 &smc->cs[2].setup);
98
99 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
100 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
101 &smc->cs[2].pulse);
102
103 writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
104 &smc->cs[2].cycle);
105
106 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
107 AT91_SMC_MODE_EXNW_DISABLE |
108 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
109 AT91_SMC_MODE_TDF_CYCLE(1),
110 &smc->cs[2].mode);
Ilko Iliev32949232009-06-12 21:20:39 +0200111
112 /* Configure Interrupt pin as input, no pull-up */
Asen Dimovf47316a2011-07-26 04:48:41 +0000113 writel(1 << ATMEL_ID_PIOA, &pmc->pcer);
Asen Dimove3150c72010-04-06 16:18:04 +0300114 at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
Ilko Iliev32949232009-06-12 21:20:39 +0200115}
116#endif
117
118#ifdef CONFIG_LCD
119vidinfo_t panel_info = {
Jeroen Hofsteec346e462014-06-10 00:16:23 +0200120 .vl_col = 240,
121 .vl_row = 320,
122 .vl_clk = 4965000,
123 .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
124 ATMEL_LCDC_INVFRAME_INVERTED,
125 .vl_bpix = 3,
126 .vl_tft = 1,
127 .vl_hsync_len = 5,
128 .vl_left_margin = 1,
129 .vl_right_margin = 33,
130 .vl_vsync_len = 1,
131 .vl_upper_margin = 1,
132 .vl_lower_margin = 0,
133 .mmio = ATMEL_BASE_LCDC,
Ilko Iliev32949232009-06-12 21:20:39 +0200134};
135
136void lcd_enable(void)
137{
Asen Dimove3150c72010-04-06 16:18:04 +0300138 at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power up */
Ilko Iliev32949232009-06-12 21:20:39 +0200139}
140
141void lcd_disable(void)
142{
Asen Dimove3150c72010-04-06 16:18:04 +0300143 at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power down */
Ilko Iliev32949232009-06-12 21:20:39 +0200144}
145
146static void pm9261_lcd_hw_init(void)
147{
Asen Dimovf47316a2011-07-26 04:48:41 +0000148 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
Ilko Iliev32949232009-06-12 21:20:39 +0200149
Asen Dimove3150c72010-04-06 16:18:04 +0300150 at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */
151 at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */
152 at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* LCDDEN */
153 at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* LCDCC */
154 at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* LCDD2 */
155 at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* LCDD3 */
156 at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* LCDD4 */
157 at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* LCDD5 */
158 at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* LCDD6 */
159 at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* LCDD7 */
160 at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* LCDD10 */
161 at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* LCDD11 */
162 at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* LCDD12 */
163 at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* LCDD13 */
164 at91_set_a_periph(AT91_PIO_PORTB, 19, 0); /* LCDD14 */
165 at91_set_a_periph(AT91_PIO_PORTB, 20, 0); /* LCDD15 */
166 at91_set_b_periph(AT91_PIO_PORTB, 23, 0); /* LCDD18 */
167 at91_set_b_periph(AT91_PIO_PORTB, 24, 0); /* LCDD19 */
168 at91_set_b_periph(AT91_PIO_PORTB, 25, 0); /* LCDD20 */
169 at91_set_b_periph(AT91_PIO_PORTB, 26, 0); /* LCDD21 */
170 at91_set_b_periph(AT91_PIO_PORTB, 27, 0); /* LCDD22 */
171 at91_set_b_periph(AT91_PIO_PORTB, 28, 0); /* LCDD23 */
172
173 writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */
Ilko Iliev32949232009-06-12 21:20:39 +0200174
Asen Dimovf47316a2011-07-26 04:48:41 +0000175 gd->fb_base = ATMEL_BASE_SRAM;
Ilko Iliev32949232009-06-12 21:20:39 +0200176}
177
178#ifdef CONFIG_LCD_INFO
179#include <nand.h>
180#include <version.h>
181
182extern flash_info_t flash_info[];
183
184void lcd_show_board_info(void)
185{
186 ulong dram_size, nand_size, flash_size, dataflash_size;
187 int i;
188 char temp[32];
189
190 lcd_printf ("%s\n", U_BOOT_VERSION);
191 lcd_printf ("(C) 2009 Ronetix GmbH\n");
192 lcd_printf ("support@ronetix.at\n");
193 lcd_printf ("%s CPU at %s MHz",
Achim Ehrlich7c966a82010-02-24 10:29:16 +0100194 CONFIG_SYS_AT91_CPU_NAME,
Ilko Iliev32949232009-06-12 21:20:39 +0200195 strmhz(temp, get_cpu_clk_rate()));
196
197 dram_size = 0;
198 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
199 dram_size += gd->bd->bi_dram[i].size;
200
201 nand_size = 0;
202 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
203 nand_size += nand_info[i].size;
204
205 flash_size = 0;
206 for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
207 flash_size += flash_info[i].size;
208
209 dataflash_size = 0;
210 for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++)
211 dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number *
212 dataflash_info[i].Device.pages_size;
213
214 lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n"
215 "%ld MB DataFlash\n",
216 dram_size >> 20,
217 nand_size >> 20,
218 flash_size >> 20,
219 dataflash_size >> 20);
220}
221#endif /* CONFIG_LCD_INFO */
222
223#endif /* CONFIG_LCD */
224
Asen Dimov0160c1e2011-12-09 10:59:07 +0000225int board_early_init_f(void)
Ilko Iliev32949232009-06-12 21:20:39 +0200226{
Asen Dimovf47316a2011-07-26 04:48:41 +0000227 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
Asen Dimove3150c72010-04-06 16:18:04 +0300228
Asen Dimov0160c1e2011-12-09 10:59:07 +0000229 /* Enable clocks for some PIOs */
Asen Dimovf47316a2011-07-26 04:48:41 +0000230 writel(1 << ATMEL_ID_PIOA |
231 1 << ATMEL_ID_PIOC,
Asen Dimove3150c72010-04-06 16:18:04 +0300232 &pmc->pcer);
Ilko Iliev32949232009-06-12 21:20:39 +0200233
Asen Dimov0160c1e2011-12-09 10:59:07 +0000234 at91_seriald_hw_init();
235
236 return 0;
237}
238
239int board_init(void)
240{
241 /* arch number of PM9261-Board */
242 gd->bd->bi_arch_number = MACH_TYPE_PM9261;
243
Ilko Iliev32949232009-06-12 21:20:39 +0200244 /* adress of boot parameters */
245 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
246
Ilko Iliev32949232009-06-12 21:20:39 +0200247#ifdef CONFIG_CMD_NAND
248 pm9261_nand_hw_init();
249#endif
250#ifdef CONFIG_HAS_DATAFLASH
251 at91_spi0_hw_init(1 << 0);
252#endif
253#ifdef CONFIG_DRIVER_DM9000
254 pm9261_dm9000_hw_init();
255#endif
256#ifdef CONFIG_LCD
257 pm9261_lcd_hw_init();
258#endif
259 return 0;
260}
261
Ilko Ilieve830b662009-09-05 02:51:34 +0200262#ifdef CONFIG_DRIVER_DM9000
263int board_eth_init(bd_t *bis)
264{
265 return dm9000_initialize(bis);
266}
267#endif
268
Ilko Iliev32949232009-06-12 21:20:39 +0200269int dram_init(void)
270{
Asen Dimov4f81bf42010-12-12 12:41:30 +0200271 /* dram_init must store complete ramsize in gd->ram_size */
Albert ARIBAUDa55d23c2011-07-03 05:55:33 +0000272 gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
Asen Dimov4f81bf42010-12-12 12:41:30 +0200273 PHYS_SDRAM_SIZE);
274 return 0;
275}
276
277void dram_init_banksize(void)
278{
Ilko Iliev32949232009-06-12 21:20:39 +0200279 gd->bd->bi_dram[0].start = PHYS_SDRAM;
280 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
Ilko Iliev32949232009-06-12 21:20:39 +0200281}
282
283#ifdef CONFIG_RESET_PHY_R
284void reset_phy(void)
285{
286#ifdef CONFIG_DRIVER_DM9000
287 /*
288 * Initialize ethernet HW addr prior to starting Linux,
289 * needed for nfsroot
290 */
291 eth_init(gd->bd);
292#endif
293}
294#endif
295
296#ifdef CONFIG_DISPLAY_BOARDINFO
297int checkboard (void)
298{
299 char buf[32];
300
301 printf ("Board : Ronetix PM9261\n");
302 printf ("Crystal frequency: %8s MHz\n",
303 strmhz(buf, get_main_clk_rate()));
304 printf ("CPU clock : %8s MHz\n",
305 strmhz(buf, get_cpu_clk_rate()));
306 printf ("Master clock : %8s MHz\n",
307 strmhz(buf, get_mck_clk_rate()));
308
309 return 0;
310}
311#endif