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gerrit.cesnet.cz / github / trini / u-boot / c346cf13509c9bfcd98c679a9822bb346432b9b6 / . / arch / powerpc / cpu / mpc85xx / t2080_serdes.c
blob: 07e27deb1f1a99faf6423ab3ca752d7da9b444f6 [file] [log] [blame]
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800[diff] [blame]1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#include <common.h>
10#include <asm/fsl_serdes.h>
11#include <asm/processor.h>
12#include "fsl_corenet2_serdes.h"
13
14struct serdes_config {
15 u32 protocol;
16 u8 lanes[SRDS_MAX_LANES];
17};
18
19static const struct serdes_config serdes1_cfg_tbl[] = {
20 /* SerDes 1 */
21 {0x6E, {XFI_FM1_MAC9, XFI_FM1_MAC10,
22 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
23 PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
24 {0xBC, {PCIE3, PCIE3, SGMII_FM1_DTSEC1,
25 SGMII_FM1_DTSEC2, PCIE4, PCIE4, PCIE4, PCIE4} },
26 {0xC8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
27 SGMII_FM1_DTSEC2, PCIE4, PCIE4,
28 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
29 {0xD6, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
30 SGMII_FM1_DTSEC2, PCIE4, PCIE4,
31 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
32 {0xDE, {PCIE3, PCIE3, PCIE3, PCIE3,
33 PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
34 {0xE0, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4,
35 PCIE1, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
36 {0xF2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
37 SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
38 {0xF8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
39 SGMII_FM1_DTSEC2, PCIE4, PCIE1, PCIE2, SGMII_FM1_DTSEC6} },
40 {0xFA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
41 SGMII_FM1_DTSEC2, PCIE4, PCIE1,
42 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
43 {0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
44 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
45 PCIE4, PCIE4, PCIE4, PCIE4} },
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800[diff] [blame]46 {0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
47 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
48 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
49 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
50 {0x95, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
51 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
52 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
53 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
54 {0xA2, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
55 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
56 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
57 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
58 {0x94, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
59 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
60 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
61 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
62 {0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
63 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
64 PCIE4, SGMII_FM1_DTSEC4,
65 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
66 {0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
67 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
68 PCIE4, SGMII_FM1_DTSEC4,
69 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
70 {0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
71 HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
72 PCIE4, SGMII_FM1_DTSEC4,
73 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
74 {0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10,
75 XFI_FM1_MAC1, XFI_FM1_MAC2,
76 PCIE4, SGMII_FM1_DTSEC4,
77 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
78 {0x6D, {XFI_FM1_MAC9, XFI_FM1_MAC10,
79 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
80 PCIE4, PCIE4, PCIE4, PCIE4} },
81 {0x71, {XFI_FM1_MAC9, XFI_FM1_MAC10,
82 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
83 SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
84 {0xA6, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
85 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
86 PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
87 {0x8E, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
88 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
89 PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
90 {0x8F, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
91 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, PCIE4,
92 PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
93 {0x82, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
94 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
95 PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
96 {0x83, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
97 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
98 PCIE4, PCIE4, SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
99 {0xA4, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
100 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
101 PCIE4, PCIE4, PCIE4, PCIE4} },
102 {0x96, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
103 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
104 PCIE4, PCIE4, PCIE4, PCIE4} },
105 {0x8A, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
106 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
107 PCIE4, PCIE4, PCIE4, PCIE4} },
108 {0x67, {XFI_FM1_MAC9, XFI_FM1_MAC10,
109 XFI_FM1_MAC1, XFI_FM1_MAC2,
110 PCIE4, PCIE4, PCIE4, PCIE4} },
111 {0xAB, {PCIE3, PCIE3, PCIE3, PCIE3,
112 PCIE4, PCIE4, PCIE4, PCIE4} },
113 {0xDA, {PCIE3, PCIE3, PCIE3, PCIE3,
114 PCIE3, PCIE3, PCIE3, PCIE3} },
115 {0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
116 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
117 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
118 {0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
119 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
120 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
121 {0xCB, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
122 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
123 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
124 {0xD8, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
125 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
126 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
127 {0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10,
128 XFI_FM1_MAC1, XFI_FM1_MAC2,
129 PCIE4, PCIE4, PCIE4, PCIE4} },
130
Shengzhou Liu35c471e2014-01-21 14:11:47 +0800[diff] [blame]131#if defined(CONFIG_PPC_T2081)
Shengzhou Liu629d6b32013-11-22 17:39:10 +0800[diff] [blame]132 {0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
133 PCIE4, PCIE4, PCIE4, PCIE4} },
134 {0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
135 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
136 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
137 {0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1,
138 SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
139 SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
140#endif
141 {}
142};
143
144#ifndef CONFIG_PPC_T2081
145static const struct serdes_config serdes2_cfg_tbl[] = {
146 /* SerDes 2 */
147 {0x1F, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
148 {0x16, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
149 {0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
150 {0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
151 {0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
152 {0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
153 {0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },
154 {0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
155 {0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
156 {}
157};
158#endif
159
160static const struct serdes_config *serdes_cfg_tbl[] = {
161 serdes1_cfg_tbl,
162#ifndef CONFIG_PPC_T2081
163 serdes2_cfg_tbl,
164#endif
165};
166
167enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
168{
169 const struct serdes_config *ptr;
170
171 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
172 return 0;
173
174 ptr = serdes_cfg_tbl[serdes];
175 while (ptr->protocol) {
176 if (ptr->protocol == cfg)
177 return ptr->lanes[lane];
178 ptr++;
179 }
180 return 0;
181}
182
183int is_serdes_prtcl_valid(int serdes, u32 prtcl)
184{
185 int i;
186 const struct serdes_config *ptr;
187
188 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
189 return 0;
190
191 ptr = serdes_cfg_tbl[serdes];
192 while (ptr->protocol) {
193 if (ptr->protocol == prtcl)
194 break;
195 ptr++;
196 }
197
198 if (!ptr->protocol)
199 return 0;
200
201 for (i = 0; i < SRDS_MAX_LANES; i++) {
202 if (ptr->lanes[i] != NONE)
203 return 1;
204 }
205
206 return 0;
207}