blob: 19e1ebdb1d6a3e82d1149c15084635fb73f4de70 [file] [log] [blame]
Michal Simek64eb13b2019-04-12 12:19:22 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller
4 *
5 * (C) Copyright 2019, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9/dts-v1/;
10
11#include "zynqmp.dtsi"
12#include "zynqmp-clk-ccf.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 model = "Versal System Controller on a2197 Memory Char board RevA";
Michal Simek50d92832019-06-28 13:16:10 +020017 compatible = "xlnx,zynqmp-m-a2197-01-revA", "xlnx,zynqmp-a2197-revA",
Michal Simek64eb13b2019-04-12 12:19:22 +020018 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
19
20 aliases {
21 ethernet0 = &gem0;
22 gpio0 = &gpio;
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 mmc0 = &sdhci0;
26 mmc1 = &sdhci1;
27 rtc0 = &rtc;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 serial2 = &dcc;
31 usb0 = &usb0;
32 usb1 = &usb1;
33 spi0 = &qspi;
34 };
35
36 chosen {
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
39 xlnx,eeprom = <&eeprom>;
40 };
41
42 memory@0 {
43 device_type = "memory";
44 reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
45 };
Michal Simekeaf96b12019-08-26 11:09:54 +020046
47 ina226-vcc-aux {
48 compatible = "iio-hwmon";
49 io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>;
50 };
51 ina226-vcc-ram {
52 compatible = "iio-hwmon";
53 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
54 };
55 ina226-vcc1v1-lp4 {
56 compatible = "iio-hwmon";
57 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
58 };
59 ina226-vcc1v2-lp4 {
60 compatible = "iio-hwmon";
61 io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>;
62 };
63 ina226-vdd1-1v8-lp4 {
64 compatible = "iio-hwmon";
65 io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
66 };
67 ina226-vcc0v6-lp4 {
68 compatible = "iio-hwmon";
69 io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>;
70 };
Michal Simek64eb13b2019-04-12 12:19:22 +020071};
72
73&qspi {
74 status = "okay";
75 is-dual = <1>;
76 flash@0 {
Michal Simekb954e882019-08-07 09:58:29 +020077 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
Michal Simek64eb13b2019-04-12 12:19:22 +020078 #address-cells = <1>;
79 #size-cells = <1>;
80 reg = <0x0>;
81 spi-tx-bus-width = <1>;
82 spi-rx-bus-width = <4>;
83 spi-max-frequency = <108000000>;
84 };
85};
86
87&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
88 status = "okay";
89 non-removable;
90 disable-wp;
91 bus-width = <8>;
Michal Simek01a6da12020-07-22 17:42:43 +020092 xlnx,mio-bank = <0>; /* FIXME tap delay */
Michal Simek64eb13b2019-04-12 12:19:22 +020093};
94
95&uart0 { /* uart0 MIO38-39 */
96 status = "okay";
97 u-boot,dm-pre-reloc;
98};
99
100&uart1 { /* uart1 MIO40-41 */
101 status = "okay";
102 u-boot,dm-pre-reloc;
103};
104
105&sdhci1 { /* sd1 MIO45-51 cd in place */
106 status = "disable";
107 no-1-8-v;
108 disable-wp;
Michal Simek01a6da12020-07-22 17:42:43 +0200109 xlnx,mio-bank = <1>;
Michal Simek64eb13b2019-04-12 12:19:22 +0200110};
111
112&gem0 {
113 status = "okay";
114 phy-handle = <&phy0>;
115 phy-mode = "sgmii"; /* DTG generates this properly 1512 */
116 phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
Michal Simek2975a422019-08-08 12:44:22 +0200117 phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
Michal Simek64eb13b2019-04-12 12:19:22 +0200118 reg = <0>;
119/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
120 };
Michal Simek64eb13b2019-04-12 12:19:22 +0200121};
122
123&gpio {
124 status = "okay";
125 gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */
126 "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */
127 "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
128 "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
129 "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
130 "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */
131 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
132 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
133 "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
134 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
135 "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
136 "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
137 "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
138 "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
139 "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
140 "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
141 "", "", "", "", "", /* 78 - 79 */
142 "", "", "", "", "", /* 80 - 84 */
143 "", "", "", "", "", /* 85 -89 */
144 "", "", "", "", "", /* 90 - 94 */
145 "", "", "", "", "", /* 95 - 99 */
146 "", "", "", "", "", /* 100 - 104 */
147 "", "", "", "", "", /* 105 - 109 */
148 "", "", "", "", "", /* 110 - 114 */
149 "", "", "", "", "", /* 115 - 119 */
150 "", "", "", "", "", /* 120 - 124 */
151 "", "", "", "", "", /* 125 - 129 */
152 "", "", "", "", "", /* 130 - 134 */
153 "", "", "", "", "", /* 135 - 139 */
154 "", "", "", "", "", /* 140 - 144 */
155 "", "", "", "", "", /* 145 - 149 */
156 "", "", "", "", "", /* 150 - 154 */
157 "", "", "", "", "", /* 155 - 159 */
158 "", "", "", "", "", /* 160 - 164 */
159 "", "", "", "", "", /* 165 - 169 */
160 "", "", "", ""; /* 170 - 174 */
161};
162
163&i2c0 { /* MIO 34-35 - can't stay here */
164 status = "okay";
165 clock-frequency = <400000>;
166 i2c-mux@74 { /* u46 */
167 compatible = "nxp,pca9548";
168 #address-cells = <1>;
169 #size-cells = <0>;
170 reg = <0x74>;
171 /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
172 i2c@0 { /* PMBUS must be enabled via SW21 */
173 #address-cells = <1>;
174 #size-cells = <0>;
175 reg = <0>;
176 reg_vcc1v2_lp4: tps544@15 { /* u97 */
177 compatible = "ti,tps544b25";
178 reg = <0x15>;
179 };
180 reg_vcc1v1_lp4: tps544@16 { /* u95 */
181 compatible = "ti,tps544b25";
182 reg = <0x16>;
183 };
184 reg_vdd1_1v8_lp4: tps544@17 { /* u99 */
185 compatible = "ti,tps544b25";
186 reg = <0x17>;
187 };
188 /* UTIL_PMBUS connection */
189 reg_vcc1v8: tps544@13 { /* u92 */
190 compatible = "ti,tps544b25";
191 reg = <0x13>;
192 };
193 reg_vcc3v3: tps544@14 { /* u93 */
194 compatible = "ti,tps544b25";
195 reg = <0x14>;
196 };
197 reg_vcc5v0: tps544@1e { /* u94 */
198 compatible = "ti,tps544b25";
199 reg = <0x1e>;
200 };
201 };
202 i2c@1 { /* PMBUS_INA226 */
203 #address-cells = <1>;
204 #size-cells = <0>;
205 reg = <1>;
206 vcc_aux: ina226@42 { /* u86 */
207 compatible = "ti,ina226";
Michal Simekeaf96b12019-08-26 11:09:54 +0200208 #io-channel-cells = <1>;
Michal Simek33aaa092019-08-26 11:10:48 +0200209 label = "ina226-vcc-aux";
Michal Simek64eb13b2019-04-12 12:19:22 +0200210 reg = <0x42>;
211 shunt-resistor = <5000>;
212 };
213 vcc_ram: ina226@43 { /* u81 */
214 compatible = "ti,ina226";
Michal Simekeaf96b12019-08-26 11:09:54 +0200215 #io-channel-cells = <1>;
Michal Simek33aaa092019-08-26 11:10:48 +0200216 label = "ina226-vcc-ram";
Michal Simek64eb13b2019-04-12 12:19:22 +0200217 reg = <0x43>;
218 shunt-resistor = <5000>;
219 };
220 vcc1v1_lp4: ina226@46 { /* u96 */
221 compatible = "ti,ina226";
Michal Simekeaf96b12019-08-26 11:09:54 +0200222 #io-channel-cells = <1>;
Michal Simek33aaa092019-08-26 11:10:48 +0200223 label = "ina226-vcc1v1-lp4";
Michal Simek64eb13b2019-04-12 12:19:22 +0200224 reg = <0x46>;
225 shunt-resistor = <5000>;
226 };
227 vcc1v2_lp4: ina226@47 { /* u98 */
228 compatible = "ti,ina226";
Michal Simekeaf96b12019-08-26 11:09:54 +0200229 #io-channel-cells = <1>;
Michal Simek33aaa092019-08-26 11:10:48 +0200230 label = "ina226-vcc1v2-lp4";
Michal Simek64eb13b2019-04-12 12:19:22 +0200231 reg = <0x47>;
232 shunt-resistor = <5000>;
233 };
234 vdd1_1v8_lp4: ina226@48 { /* u100 */
235 compatible = "ti,ina226";
Michal Simekeaf96b12019-08-26 11:09:54 +0200236 #io-channel-cells = <1>;
Michal Simek33aaa092019-08-26 11:10:48 +0200237 label = "ina226-vdd1-1v8-lp4";
Michal Simek64eb13b2019-04-12 12:19:22 +0200238 reg = <0x48>;
239 shunt-resistor = <5000>;
240 };
241 vcc0v6_lp4: ina226@49 { /* u101 */
242 compatible = "ti,ina226";
Michal Simekeaf96b12019-08-26 11:09:54 +0200243 #io-channel-cells = <1>;
Michal Simek33aaa092019-08-26 11:10:48 +0200244 label = "ina226-vcc0v6-lp4";
Michal Simek64eb13b2019-04-12 12:19:22 +0200245 reg = <0x49>;
246 shunt-resistor = <5000>;
247 };
248 };
249 i2c@2 { /* PMBUS1 */
250 #address-cells = <1>;
251 #size-cells = <0>;
252 reg = <2>;
253 reg_vccint: tps53681@c0 { /* u69 */
Nishant Mittalebb28f22019-07-24 14:58:52 +0530254 compatible = "ti,tps53681", "ti,tps53679";
Michal Simek64eb13b2019-04-12 12:19:22 +0200255 reg = <0xc0>;
256 };
257 reg_vcc_pmc: tps544@7 { /* u80 */
258 compatible = "ti,tps544b25";
259 reg = <0x7>;
260 };
261 reg_vcc_ram: tps544@8 { /* u82 */
262 compatible = "ti,tps544b25";
263 reg = <0x8>;
264 };
265 reg_vcc_pslp: tps544@9 { /* u83 */
266 compatible = "ti,tps544b25";
267 reg = <0x9>;
268 };
269 reg_vcc_psfp: tps544@a { /* u84 */
270 compatible = "ti,tps544b25";
271 reg = <0xa>;
272 };
273 reg_vccaux: tps544@d { /* u85 */
274 compatible = "ti,tps544b25";
275 reg = <0xd>;
276 };
277 reg_vccaux_pmc: tps544@e { /* u87 */
278 compatible = "ti,tps544b25";
279 reg = <0xe>;
280 };
281 reg_vcco_500: tps544@f { /* u88 */
282 compatible = "ti,tps544b25";
283 reg = <0xf>;
284 };
285 reg_vcco_501: tps544@10 { /* u89 */
286 compatible = "ti,tps544b25";
287 reg = <0x10>;
288 };
289 reg_vcco_502: tps544@11 { /* u90 */
290 compatible = "ti,tps544b25";
291 reg = <0x11>;
292 };
293 reg_vcco_503: tps544@12 { /* u91 */
294 compatible = "ti,tps544b25";
295 reg = <0x12>;
296 };
297 };
298 i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
299 #address-cells = <1>;
300 #size-cells = <0>;
301 /* reg = <3>; */
302 };
303 i2c@4 { /* LP_I2C_SM */
304 #address-cells = <1>;
305 #size-cells = <0>;
306 reg = <4>;
307 /* connected to U20G */
308 };
309 /* 5-7 unused */
310 };
311};
312
313/* TODO sysctrl via J239 */
314/* TODO samtec J212G/H via J242 */
315/* TODO teensy via U30 PCA9543A bus 1 */
316&i2c1 { /* i2c1 MIO 36-37 */
317 status = "okay";
318 clock-frequency = <400000>;
319
320 /* Must be enabled via J242 */
321 eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
322 compatible = "atmel,24c02";
323 reg = <0x51>;
324 };
325
Michal Simek2703d4b2019-06-28 13:52:09 +0200326 i2c-mux@74 { /* u47 */
Michal Simek64eb13b2019-04-12 12:19:22 +0200327 compatible = "nxp,pca9548";
328 #address-cells = <1>;
329 #size-cells = <0>;
330 reg = <0x74>;
331 /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */
332 dc_i2c: i2c@0 { /* DC_I2C */
333 #address-cells = <1>;
334 #size-cells = <0>;
335 reg = <0>;
336 /* Use for storing information about SC board */
337 eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */
338 compatible = "atmel,24c08";
339 reg = <0x54>;
340 };
341 si570_ref_clk: clock-generator@5d { /* u26 */
342 #clock-cells = <0>;
343 compatible = "silabs,si570";
344 reg = <0x5d>; /* FIXME addr */
345 temperature-stability = <50>;
346 factory-fout = <156250000>; /* FIXME every chip can be different */
347 clock-frequency = <33333333>;
348 clock-output-names = "REF_CLK"; /* FIXME */
349 };
350 /* Connection via Samtec U20D */
351 /* Use for storing information about X-PRC card */
352 x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
353 compatible = "atmel,24c02";
354 reg = <0x52>;
355 };
356
357 /* Use for setting up certain features on X-PRC card */
358 x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
359 compatible = "nxp,pca9534";
360 reg = <0x22>;
361 gpio-controller; /* IRQ not connected */
362 #gpio-cells = <2>;
363 gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
364 "", "", "", "";
365 gtr_sel0 {
366 gpio-hog;
367 gpios = <0 0>;
368 input; /* FIXME add meaning */
369 line-name = "sw4_1";
370 };
371 gtr_sel1 {
372 gpio-hog;
373 gpios = <1 0>;
374 input; /* FIXME add meaning */
375 line-name = "sw4_2";
376 };
377 gtr_sel2 {
378 gpio-hog;
379 gpios = <2 0>;
380 input; /* FIXME add meaning */
381 line-name = "sw4_3";
382 };
383 gtr_sel3 {
384 gpio-hog;
385 gpios = <3 0>;
386 input; /* FIXME add meaning */
387 line-name = "sw4_4";
388 };
389 };
390 };
Michal Simek64eb13b2019-04-12 12:19:22 +0200391 i2c@2 { /* C0_LP4 */
392 #address-cells = <1>;
393 #size-cells = <0>;
394 reg = <2>;
Michal Simek2703d4b2019-06-28 13:52:09 +0200395 si570_c0_lp4: clock-generator@55 { /* u10 */
Michal Simek64eb13b2019-04-12 12:19:22 +0200396 #clock-cells = <0>;
397 compatible = "silabs,si570";
Michal Simek2703d4b2019-06-28 13:52:09 +0200398 reg = <0x55>;
Michal Simek64eb13b2019-04-12 12:19:22 +0200399 temperature-stability = <50>;
400 factory-fout = <30000000>;
401 clock-frequency = <30000000>;
402 clock-output-names = "C0_LP4_SI570_CLK";
403 };
404 };
405 i2c@3 { /* C1_LP4 */
406 #address-cells = <1>;
407 #size-cells = <0>;
408 reg = <3>;
409 si570_c1_lp4: clock-generator@5d { /* u10 */
410 #clock-cells = <0>;
411 compatible = "silabs,si570";
412 reg = <0x5d>; /* FIXME addr */
413 temperature-stability = <50>;
414 factory-fout = <30000000>;
415 clock-frequency = <30000000>;
416 clock-output-names = "C1_LP4_SI570_CLK";
417 };
418 };
419 i2c@4 { /* C2_LP4 */
420 #address-cells = <1>;
421 #size-cells = <0>;
422 reg = <4>;
Michal Simek2703d4b2019-06-28 13:52:09 +0200423 si570_c2_lp4: clock-generator@55 { /* u10 */
Michal Simek64eb13b2019-04-12 12:19:22 +0200424 #clock-cells = <0>;
425 compatible = "silabs,si570";
Michal Simek2703d4b2019-06-28 13:52:09 +0200426 reg = <0x55>;
Michal Simek64eb13b2019-04-12 12:19:22 +0200427 temperature-stability = <50>;
428 factory-fout = <30000000>;
429 clock-frequency = <30000000>;
430 clock-output-names = "C2_LP4_SI570_CLK";
431 };
432 };
433 i2c@5 { /* C3_LP4 */
434 #address-cells = <1>;
435 #size-cells = <0>;
436 reg = <5>;
Michal Simek2703d4b2019-06-28 13:52:09 +0200437 si570_c3_lp4: clock-generator@55 { /* u15 */
Michal Simek64eb13b2019-04-12 12:19:22 +0200438 #clock-cells = <0>;
439 compatible = "silabs,si570";
Michal Simek2703d4b2019-06-28 13:52:09 +0200440 reg = <0x55>;
Michal Simek64eb13b2019-04-12 12:19:22 +0200441 temperature-stability = <50>;
442 factory-fout = <30000000>;
443 clock-frequency = <30000000>;
444 clock-output-names = "C3_LP4_SI570_CLK";
445 };
446 };
447 i2c@6 { /* HSDP_SI570 */
448 #address-cells = <1>;
449 #size-cells = <0>;
450 reg = <6>;
451 si570_hsdp: clock-generator@5d { /* u19 */
452 #clock-cells = <0>;
453 compatible = "silabs,si570";
454 reg = <0x5d>; /* FIXME addr */
455 temperature-stability = <50>;
Michal Simek2703d4b2019-06-28 13:52:09 +0200456 factory-fout = <156250000>;
457 clock-frequency = <156250000>;
Michal Simek64eb13b2019-04-12 12:19:22 +0200458 clock-output-names = "HSDP_SI570";
459 };
460 };
461 };
462};
463
464&usb0 {
465 status = "okay";
466 xlnx,usb-polarity = <0>;
467 xlnx,usb-reset-mode = <0>;
468};
469
470&dwc3_0 {
471 status = "okay";
472 dr_mode = "host";
473 /* dr_mode = "peripheral"; */
474 maximum-speed = "high-speed";
475};
476
477&usb1 {
478 status = "disabled"; /* not at mem board */
479 xlnx,usb-polarity = <0>;
480 xlnx,usb-reset-mode = <0>;
481};
482
483&dwc3_1 {
484 /delete-property/ phy-names ;
485 /delete-property/ phys ;
486 maximum-speed = "high-speed";
487 snps,dis_u2_susphy_quirk ;
488 snps,dis_u3_susphy_quirk ;
489 status = "disabled";
490};