Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: Intel |
Simon Glass | 3a1a18f | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2013, Intel Corporation |
| 4 | * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 5 | * Copyright (C) 2015, Kodak Alaris, Inc |
Simon Glass | 3a1a18f | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 9 | #include <fdtdec.h> |
Simon Glass | f7ae49f | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 10 | #include <log.h> |
Simon Glass | 8331188 | 2019-09-25 08:00:11 -0600 | [diff] [blame] | 11 | #include <asm/fsp1/fsp_support.h> |
Simon Glass | 401d1c4 | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 12 | #include <asm/global_data.h> |
Simon Glass | 3a1a18f | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 13 | |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 14 | DECLARE_GLOBAL_DATA_PTR; |
| 15 | |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 16 | /** |
Bin Meng | f685955 | 2017-10-13 01:30:05 -0700 | [diff] [blame] | 17 | * Override the FSP's Azalia configuration data |
| 18 | * |
| 19 | * @azalia: pointer to be updated to point to a ROM address where Azalia |
| 20 | * configuration data is stored |
| 21 | */ |
Bin Meng | 83262f9 | 2017-10-13 01:30:06 -0700 | [diff] [blame] | 22 | __weak void update_fsp_azalia_configs(struct azalia_config **azalia) |
Bin Meng | f685955 | 2017-10-13 01:30:05 -0700 | [diff] [blame] | 23 | { |
Bin Meng | 83262f9 | 2017-10-13 01:30:06 -0700 | [diff] [blame] | 24 | *azalia = NULL; |
Bin Meng | f685955 | 2017-10-13 01:30:05 -0700 | [diff] [blame] | 25 | } |
| 26 | |
| 27 | /** |
Bin Meng | 81f84aa | 2015-12-10 22:03:00 -0800 | [diff] [blame] | 28 | * Override the FSP's configuration data. |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 29 | * If the device tree does not specify an integer setting, use the default |
| 30 | * provided in Intel's Baytrail_FSP_Gold4.tgz release FSP/BayleyBayFsp.bsf file. |
| 31 | */ |
Simon Glass | e2adc36 | 2019-09-25 08:11:25 -0600 | [diff] [blame] | 32 | void fsp_update_configs(struct fsp_config_data *config, |
Bin Meng | 214feec | 2015-12-10 22:03:04 -0800 | [diff] [blame] | 33 | struct fspinit_rtbuf *rt_buf) |
Simon Glass | 3a1a18f | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 34 | { |
Bin Meng | 81f84aa | 2015-12-10 22:03:00 -0800 | [diff] [blame] | 35 | struct upd_region *fsp_upd = &config->fsp_upd; |
Simon Glass | 3a1a18f | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 36 | struct memory_down_data *mem; |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 37 | const void *blob = gd->fdt_blob; |
| 38 | int node; |
Simon Glass | 3a1a18f | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 39 | |
Bin Meng | 214feec | 2015-12-10 22:03:04 -0800 | [diff] [blame] | 40 | /* Initialize runtime buffer for fsp_init() */ |
| 41 | rt_buf->common.stack_top = config->common.stack_top - 32; |
| 42 | rt_buf->common.boot_mode = config->common.boot_mode; |
| 43 | rt_buf->common.upd_data = &config->fsp_upd; |
| 44 | |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 45 | node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_BAYTRAIL_FSP); |
| 46 | if (node < 0) { |
| 47 | debug("%s: Cannot find FSP node\n", __func__); |
| 48 | return; |
| 49 | } |
| 50 | |
| 51 | fsp_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node, |
| 52 | "fsp,mrc-init-tseg-size", |
Bin Meng | 5e74e5a | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 53 | MRC_INIT_TSEG_SIZE_1MB); |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 54 | fsp_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node, |
| 55 | "fsp,mrc-init-mmio-size", |
Bin Meng | 5e74e5a | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 56 | MRC_INIT_MMIO_SIZE_2048MB); |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 57 | fsp_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node, |
| 58 | "fsp,mrc-init-spd-addr1", |
| 59 | 0xa0); |
| 60 | fsp_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node, |
| 61 | "fsp,mrc-init-spd-addr2", |
| 62 | 0xa2); |
| 63 | fsp_upd->emmc_boot_mode = fdtdec_get_int(blob, node, |
Bin Meng | 5e74e5a | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 64 | "fsp,emmc-boot-mode", |
| 65 | EMMC_BOOT_MODE_EMMC41); |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 66 | fsp_upd->enable_sdio = fdtdec_get_bool(blob, node, "fsp,enable-sdio"); |
| 67 | fsp_upd->enable_sdcard = fdtdec_get_bool(blob, node, |
| 68 | "fsp,enable-sdcard"); |
| 69 | fsp_upd->enable_hsuart0 = fdtdec_get_bool(blob, node, |
| 70 | "fsp,enable-hsuart0"); |
| 71 | fsp_upd->enable_hsuart1 = fdtdec_get_bool(blob, node, |
| 72 | "fsp,enable-hsuart1"); |
| 73 | fsp_upd->enable_spi = fdtdec_get_bool(blob, node, "fsp,enable-spi"); |
| 74 | fsp_upd->enable_sata = fdtdec_get_bool(blob, node, "fsp,enable-sata"); |
Bin Meng | 5e74e5a | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 75 | fsp_upd->sata_mode = fdtdec_get_int(blob, node, "fsp,sata-mode", |
| 76 | SATA_MODE_AHCI); |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 77 | fsp_upd->enable_azalia = fdtdec_get_bool(blob, node, |
| 78 | "fsp,enable-azalia"); |
Bin Meng | f685955 | 2017-10-13 01:30:05 -0700 | [diff] [blame] | 79 | if (fsp_upd->enable_azalia) |
| 80 | update_fsp_azalia_configs(&fsp_upd->azalia_cfg_ptr); |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 81 | fsp_upd->enable_xhci = fdtdec_get_bool(blob, node, "fsp,enable-xhci"); |
Bin Meng | f8f291b | 2017-05-31 01:04:15 -0700 | [diff] [blame] | 82 | fsp_upd->lpe_mode = fdtdec_get_int(blob, node, "fsp,lpe-mode", |
| 83 | LPE_MODE_PCI); |
| 84 | fsp_upd->lpss_sio_mode = fdtdec_get_int(blob, node, "fsp,lpss-sio-mode", |
| 85 | LPSS_SIO_MODE_PCI); |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 86 | fsp_upd->enable_dma0 = fdtdec_get_bool(blob, node, "fsp,enable-dma0"); |
| 87 | fsp_upd->enable_dma1 = fdtdec_get_bool(blob, node, "fsp,enable-dma1"); |
| 88 | fsp_upd->enable_i2_c0 = fdtdec_get_bool(blob, node, "fsp,enable-i2c0"); |
| 89 | fsp_upd->enable_i2_c1 = fdtdec_get_bool(blob, node, "fsp,enable-i2c1"); |
| 90 | fsp_upd->enable_i2_c2 = fdtdec_get_bool(blob, node, "fsp,enable-i2c2"); |
| 91 | fsp_upd->enable_i2_c3 = fdtdec_get_bool(blob, node, "fsp,enable-i2c3"); |
| 92 | fsp_upd->enable_i2_c4 = fdtdec_get_bool(blob, node, "fsp,enable-i2c4"); |
| 93 | fsp_upd->enable_i2_c5 = fdtdec_get_bool(blob, node, "fsp,enable-i2c5"); |
| 94 | fsp_upd->enable_i2_c6 = fdtdec_get_bool(blob, node, "fsp,enable-i2c6"); |
| 95 | fsp_upd->enable_pwm0 = fdtdec_get_bool(blob, node, "fsp,enable-pwm0"); |
| 96 | fsp_upd->enable_pwm1 = fdtdec_get_bool(blob, node, "fsp,enable-pwm1"); |
| 97 | fsp_upd->enable_hsi = fdtdec_get_bool(blob, node, "fsp,enable-hsi"); |
| 98 | fsp_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node, |
Bin Meng | 5e74e5a | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 99 | "fsp,igd-dvmt50-pre-alloc", IGD_DVMT50_PRE_ALLOC_64MB); |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 100 | fsp_upd->aperture_size = fdtdec_get_int(blob, node, "fsp,aperture-size", |
Bin Meng | 5e74e5a | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 101 | APERTURE_SIZE_256MB); |
| 102 | fsp_upd->gtt_size = fdtdec_get_int(blob, node, "fsp,gtt-size", |
| 103 | GTT_SIZE_2MB); |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 104 | fsp_upd->mrc_debug_msg = fdtdec_get_bool(blob, node, |
| 105 | "fsp,mrc-debug-msg"); |
| 106 | fsp_upd->isp_enable = fdtdec_get_bool(blob, node, "fsp,isp-enable"); |
Bin Meng | f8f291b | 2017-05-31 01:04:15 -0700 | [diff] [blame] | 107 | fsp_upd->scc_mode = fdtdec_get_int(blob, node, "fsp,scc-mode", |
| 108 | SCC_MODE_PCI); |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 109 | fsp_upd->igd_render_standby = fdtdec_get_bool(blob, node, |
| 110 | "fsp,igd-render-standby"); |
| 111 | fsp_upd->txe_uma_enable = fdtdec_get_bool(blob, node, |
| 112 | "fsp,txe-uma-enable"); |
| 113 | fsp_upd->os_selection = fdtdec_get_int(blob, node, "fsp,os-selection", |
Bin Meng | 5e74e5a | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 114 | OS_SELECTION_LINUX); |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 115 | fsp_upd->emmc45_ddr50_enabled = fdtdec_get_bool(blob, node, |
| 116 | "fsp,emmc45-ddr50-enabled"); |
| 117 | fsp_upd->emmc45_hs200_enabled = fdtdec_get_bool(blob, node, |
| 118 | "fsp,emmc45-hs200-enabled"); |
| 119 | fsp_upd->emmc45_retune_timer_value = fdtdec_get_int(blob, node, |
| 120 | "fsp,emmc45-retune-timer-value", 8); |
| 121 | fsp_upd->enable_igd = fdtdec_get_bool(blob, node, "fsp,enable-igd"); |
Simon Glass | 3a1a18f | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 122 | |
| 123 | mem = &fsp_upd->memory_params; |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 124 | mem->enable_memory_down = fdtdec_get_bool(blob, node, |
| 125 | "fsp,enable-memory-down"); |
| 126 | if (mem->enable_memory_down) { |
| 127 | node = fdtdec_next_compatible(blob, node, |
| 128 | COMPAT_INTEL_BAYTRAIL_FSP_MDP); |
| 129 | if (node < 0) { |
| 130 | debug("%s: Cannot find FSP memory-down-params node\n", |
| 131 | __func__); |
| 132 | } else { |
| 133 | mem->dram_speed = fdtdec_get_int(blob, node, |
| 134 | "fsp,dram-speed", |
Bin Meng | 5e74e5a | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 135 | DRAM_SPEED_1333MTS); |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 136 | mem->dram_type = fdtdec_get_int(blob, node, |
Bin Meng | 5e74e5a | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 137 | "fsp,dram-type", |
| 138 | DRAM_TYPE_DDR3L); |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 139 | mem->dimm_0_enable = fdtdec_get_bool(blob, node, |
| 140 | "fsp,dimm-0-enable"); |
| 141 | mem->dimm_1_enable = fdtdec_get_bool(blob, node, |
| 142 | "fsp,dimm-1-enable"); |
| 143 | mem->dimm_width = fdtdec_get_int(blob, node, |
| 144 | "fsp,dimm-width", |
Bin Meng | 5e74e5a | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 145 | DIMM_WIDTH_X8); |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 146 | mem->dimm_density = fdtdec_get_int(blob, node, |
| 147 | "fsp,dimm-density", |
Bin Meng | 5e74e5a | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 148 | DIMM_DENSITY_2GBIT); |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 149 | mem->dimm_bus_width = fdtdec_get_int(blob, node, |
Bin Meng | 5e74e5a | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 150 | "fsp,dimm-bus-width", |
| 151 | DIMM_BUS_WIDTH_64BITS); |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 152 | mem->dimm_sides = fdtdec_get_int(blob, node, |
| 153 | "fsp,dimm-sides", |
Bin Meng | 5e74e5a | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 154 | DIMM_SIDES_1RANKS); |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 155 | mem->dimm_tcl = fdtdec_get_int(blob, node, |
| 156 | "fsp,dimm-tcl", 0x09); |
| 157 | mem->dimm_trpt_rcd = fdtdec_get_int(blob, node, |
| 158 | "fsp,dimm-trpt-rcd", 0x09); |
| 159 | mem->dimm_twr = fdtdec_get_int(blob, node, |
Bin Meng | 5e74e5a | 2017-05-31 01:04:14 -0700 | [diff] [blame] | 160 | "fsp,dimm-twr", 0x0a); |
Andrew Bradford | f3b84a3 | 2015-08-07 08:36:35 -0400 | [diff] [blame] | 161 | mem->dimm_twtr = fdtdec_get_int(blob, node, |
| 162 | "fsp,dimm-twtr", 0x05); |
| 163 | mem->dimm_trrd = fdtdec_get_int(blob, node, |
| 164 | "fsp,dimm-trrd", 0x04); |
| 165 | mem->dimm_trtp = fdtdec_get_int(blob, node, |
| 166 | "fsp,dimm-trtp", 0x05); |
| 167 | mem->dimm_tfaw = fdtdec_get_int(blob, node, |
| 168 | "fsp,dimm-tfaw", 0x14); |
| 169 | } |
| 170 | } |
Simon Glass | 3a1a18f | 2015-01-27 22:13:47 -0700 | [diff] [blame] | 171 | } |