rev13@wp.pl | ed09a55 | 2015-03-01 12:44:42 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2015 |
| 3 | * Kamil Lulko, <rev13@wp.pl> |
| 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_H |
| 9 | #define __CONFIG_H |
| 10 | |
| 11 | #define CONFIG_STM32F4 |
| 12 | #define CONFIG_STM32F4DISCOVERY |
| 13 | #define CONFIG_SYS_GENERIC_BOARD |
| 14 | |
| 15 | #define CONFIG_OF_LIBFDT |
| 16 | |
| 17 | #define CONFIG_BOARD_EARLY_INIT_F |
| 18 | |
| 19 | #define CONFIG_SYS_FLASH_BASE 0x08000000 |
| 20 | |
| 21 | #define CONFIG_SYS_INIT_SP_ADDR 0x10010000 |
| 22 | #define CONFIG_SYS_TEXT_BASE 0x08000000 |
| 23 | |
| 24 | #define CONFIG_SYS_ICACHE_OFF |
| 25 | #define CONFIG_SYS_DCACHE_OFF |
| 26 | |
| 27 | /* |
| 28 | * Configuration of the external SDRAM memory |
| 29 | */ |
| 30 | #define CONFIG_NR_DRAM_BANKS 1 |
| 31 | #define CONFIG_SYS_RAM_SIZE (8 << 20) |
| 32 | #define CONFIG_SYS_RAM_CS 1 |
| 33 | #define CONFIG_SYS_RAM_FREQ_DIV 2 |
| 34 | #define CONFIG_SYS_RAM_BASE 0xD0000000 |
| 35 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE |
| 36 | #define CONFIG_SYS_LOAD_ADDR 0xD0400000 |
| 37 | #define CONFIG_LOADADDR 0xD0400000 |
| 38 | |
| 39 | #define CONFIG_SYS_MAX_FLASH_SECT 12 |
| 40 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 |
| 41 | |
| 42 | #define CONFIG_ENV_IS_IN_FLASH |
| 43 | #define CONFIG_ENV_OFFSET (256 << 10) |
| 44 | #define CONFIG_ENV_SECT_SIZE (128 << 10) |
| 45 | #define CONFIG_ENV_SIZE (8 << 10) |
| 46 | |
| 47 | #define CONFIG_BOARD_SPECIFIC_LED |
| 48 | #define CONFIG_RED_LED 110 |
| 49 | #define CONFIG_GREEN_LED 109 |
| 50 | |
| 51 | #define CONFIG_STM32_GPIO |
| 52 | #define CONFIG_STM32_SERIAL |
kunhuahuang | 60570df | 2015-04-28 03:01:19 +0800 | [diff] [blame] | 53 | /* |
| 54 | * Configuration of the USART |
| 55 | * 1: TX:PA9 PX:PA10 |
| 56 | * 2: TX:PD5 RX:PD6 |
| 57 | * 3: TX:PC10 RX:PC11 |
| 58 | * 6: TX:PC6 RX:PC7 |
| 59 | */ |
| 60 | #define CONFIG_STM32_USART 1 |
rev13@wp.pl | ed09a55 | 2015-03-01 12:44:42 +0100 | [diff] [blame] | 61 | |
| 62 | #define CONFIG_STM32_HSE_HZ 8000000 |
| 63 | |
| 64 | #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ |
| 65 | |
| 66 | #define CONFIG_CMDLINE_TAG |
| 67 | #define CONFIG_SETUP_MEMORY_TAGS |
| 68 | #define CONFIG_INITRD_TAG |
| 69 | #define CONFIG_REVISION_TAG |
| 70 | |
| 71 | #define CONFIG_SYS_CBSIZE 1024 |
| 72 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ |
| 73 | + sizeof(CONFIG_SYS_PROMPT) + 16) |
| 74 | |
| 75 | #define CONFIG_SYS_MAXARGS 16 |
| 76 | |
| 77 | #define CONFIG_SYS_MALLOC_LEN (2 << 20) |
| 78 | |
| 79 | #define CONFIG_STACKSIZE (64 << 10) |
| 80 | |
| 81 | #define CONFIG_BAUDRATE 115200 |
| 82 | #define CONFIG_BOOTARGS \ |
| 83 | "console=ttystm0,115200 earlyprintk consoleblank=0 ignore_loglevel" |
| 84 | #define CONFIG_BOOTCOMMAND \ |
| 85 | "run bootcmd_romfs" |
| 86 | |
| 87 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 88 | "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ |
| 89 | "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \ |
| 90 | "bootm 0x08044000 - 0x08042000\0" |
| 91 | |
| 92 | #define CONFIG_BOOTDELAY 3 |
| 93 | #define CONFIG_AUTOBOOT |
| 94 | |
| 95 | /* |
| 96 | * Command line configuration. |
| 97 | */ |
| 98 | #include <config_cmd_default.h> |
| 99 | |
| 100 | #define CONFIG_SYS_LONGHELP |
| 101 | #define CONFIG_SYS_HUSH_PARSER |
| 102 | #define CONFIG_SYS_PROMPT "U-Boot > " |
| 103 | #define CONFIG_AUTO_COMPLETE |
| 104 | #define CONFIG_CMDLINE_EDITING |
| 105 | |
| 106 | #define CONFIG_CMD_FLASH |
| 107 | #define CONFIG_CMD_SAVEENV |
| 108 | #define CONFIG_CMD_MEM |
| 109 | #define CONFIG_CMD_MISC |
| 110 | #define CONFIG_CMD_TIMER |
| 111 | |
| 112 | #endif /* __CONFIG_H */ |