Stefan Roese | dd58080 | 2014-10-22 12:13:18 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2014 Stefan Roese <sr@denx.de> |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef _CONFIG_DB_MV7846MP_GP_H |
| 8 | #define _CONFIG_DB_MV7846MP_GP_H |
| 9 | |
| 10 | /* |
| 11 | * High Level Configuration Options (easy to change) |
| 12 | */ |
| 13 | #define CONFIG_ARMADA_XP /* SOC Family Name */ |
Stefan Roese | 2554167 | 2015-01-19 11:33:46 +0100 | [diff] [blame] | 14 | #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ |
| 15 | |
Stefan Roese | dd58080 | 2014-10-22 12:13:18 +0200 | [diff] [blame] | 16 | #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ |
| 17 | #define CONFIG_SYS_GENERIC_BOARD |
| 18 | #define CONFIG_DISPLAY_BOARDINFO_LATE |
| 19 | |
| 20 | #define CONFIG_SYS_TEXT_BASE 0x04000000 |
| 21 | #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ |
| 22 | |
| 23 | /* |
| 24 | * Commands configuration |
| 25 | */ |
| 26 | #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ |
| 27 | #include <config_cmd_default.h> |
| 28 | #define CONFIG_CMD_DHCP |
| 29 | #define CONFIG_CMD_ENV |
| 30 | #define CONFIG_CMD_I2C |
| 31 | #define CONFIG_CMD_PING |
| 32 | #define CONFIG_CMD_SF |
| 33 | #define CONFIG_CMD_SPI |
| 34 | #define CONFIG_CMD_TFTPPUT |
| 35 | #define CONFIG_CMD_TIME |
| 36 | |
| 37 | /* I2C */ |
| 38 | #define CONFIG_SYS_I2C |
| 39 | #define CONFIG_SYS_I2C_MVTWSI |
Paul Kocialkowski | dd82242 | 2015-04-10 23:09:51 +0200 | [diff] [blame] | 40 | #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE |
Stefan Roese | dd58080 | 2014-10-22 12:13:18 +0200 | [diff] [blame] | 41 | #define CONFIG_SYS_I2C_SLAVE 0x0 |
| 42 | #define CONFIG_SYS_I2C_SPEED 100000 |
| 43 | |
| 44 | /* SPI NOR flash default params, used by sf commands */ |
| 45 | #define CONFIG_SF_DEFAULT_SPEED 1000000 |
| 46 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 |
| 47 | #define CONFIG_SPI_FLASH_STMICRO |
| 48 | |
| 49 | /* Environment in SPI NOR flash */ |
| 50 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 51 | #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ |
| 52 | #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ |
| 53 | #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ |
| 54 | |
| 55 | #define CONFIG_PHY_MARVELL /* there is a marvell phy */ |
Stefan Roese | cae9008 | 2015-04-25 06:29:52 +0200 | [diff] [blame] | 56 | #define CONFIG_PHY_ADDR { 0x10, 0x11, 0x12, 0x13 } |
Stefan Roese | dd58080 | 2014-10-22 12:13:18 +0200 | [diff] [blame] | 57 | #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII |
| 58 | #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ |
| 59 | #define CONFIG_RESET_PHY_R |
| 60 | |
| 61 | #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ |
| 62 | #define CONFIG_SYS_ALT_MEMTEST |
| 63 | |
| 64 | /* |
| 65 | * mv-common.h should be defined after CMD configs since it used them |
| 66 | * to enable certain macros |
| 67 | */ |
| 68 | #include "mv-common.h" |
| 69 | |
Stefan Roese | 2554167 | 2015-01-19 11:33:46 +0100 | [diff] [blame] | 70 | /* |
| 71 | * Memory layout while starting into the bin_hdr via the |
| 72 | * BootROM: |
| 73 | * |
| 74 | * 0x4000.4000 - 0x4003.4000 headers space (192KiB) |
| 75 | * 0x4000.4030 bin_hdr start address |
| 76 | * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) |
| 77 | * 0x4007.fffc BootROM stack top |
| 78 | * |
| 79 | * The address space between 0x4007.fffc and 0x400f.fff is not locked in |
| 80 | * L2 cache thus cannot be used. |
| 81 | */ |
| 82 | |
| 83 | /* SPL */ |
| 84 | /* Defines for SPL */ |
| 85 | #define CONFIG_SPL_FRAMEWORK |
| 86 | #define CONFIG_SPL_TEXT_BASE 0x40004030 |
| 87 | #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) |
| 88 | |
| 89 | #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) |
| 90 | #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) |
| 91 | |
| 92 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ |
| 93 | CONFIG_SPL_BSS_MAX_SIZE) |
| 94 | #define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) |
| 95 | |
| 96 | #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) |
| 97 | #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) |
| 98 | |
| 99 | #define CONFIG_SPL_LIBCOMMON_SUPPORT |
| 100 | #define CONFIG_SPL_LIBGENERIC_SUPPORT |
| 101 | #define CONFIG_SPL_SERIAL_SUPPORT |
| 102 | #define CONFIG_SPL_I2C_SUPPORT |
Stefan Roese | 2554167 | 2015-01-19 11:33:46 +0100 | [diff] [blame] | 103 | |
| 104 | /* SPL related SPI defines */ |
| 105 | #define CONFIG_SPL_SPI_SUPPORT |
| 106 | #define CONFIG_SPL_SPI_FLASH_SUPPORT |
| 107 | #define CONFIG_SPL_SPI_LOAD |
| 108 | #define CONFIG_SPL_SPI_BUS 0 |
| 109 | #define CONFIG_SPL_SPI_CS 0 |
| 110 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 |
| 111 | |
| 112 | /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ |
| 113 | #define CONFIG_SYS_MVEBU_DDR |
| 114 | #define CONFIG_SPD_EEPROM 0x4e |
| 115 | |
Stefan Roese | dd58080 | 2014-10-22 12:13:18 +0200 | [diff] [blame] | 116 | #endif /* _CONFIG_DB_MV7846MP_GP_H */ |