Mike Frysinger | 84a9dda | 2008-10-12 21:32:52 -0400 | [diff] [blame] | 1 | /* |
| 2 | * U-boot - Configuration file for BF518F EZBrd board |
| 3 | */ |
| 4 | |
| 5 | #ifndef __CONFIG_BF518F_EZBRD_H__ |
| 6 | #define __CONFIG_BF518F_EZBRD_H__ |
| 7 | |
Mike Frysinger | f348ab8 | 2009-04-24 17:22:40 -0400 | [diff] [blame] | 8 | #include <asm/config-pre.h> |
Mike Frysinger | 84a9dda | 2008-10-12 21:32:52 -0400 | [diff] [blame] | 9 | |
| 10 | |
| 11 | /* |
| 12 | * Processor Settings |
| 13 | */ |
Mike Frysinger | fbcf8e8 | 2010-12-23 14:58:37 -0500 | [diff] [blame] | 14 | #define CONFIG_BFIN_CPU bf518-0.0 |
Mike Frysinger | 84a9dda | 2008-10-12 21:32:52 -0400 | [diff] [blame] | 15 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA |
| 16 | |
| 17 | |
| 18 | /* |
| 19 | * Clock Settings |
| 20 | * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV |
| 21 | * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV |
| 22 | */ |
| 23 | /* CONFIG_CLKIN_HZ is any value in Hz */ |
| 24 | #define CONFIG_CLKIN_HZ 25000000 |
| 25 | /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ |
| 26 | /* 1 = CLKIN / 2 */ |
| 27 | #define CONFIG_CLKIN_HALF 0 |
| 28 | /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ |
| 29 | /* 1 = bypass PLL */ |
| 30 | #define CONFIG_PLL_BYPASS 0 |
| 31 | /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ |
| 32 | /* Values can range from 0-63 (where 0 means 64) */ |
| 33 | #define CONFIG_VCO_MULT 16 |
| 34 | /* CCLK_DIV controls the core clock divider */ |
| 35 | /* Values can be 1, 2, 4, or 8 ONLY */ |
| 36 | #define CONFIG_CCLK_DIV 1 |
| 37 | /* SCLK_DIV controls the system clock divider */ |
| 38 | /* Values can range from 1-15 */ |
| 39 | #define CONFIG_SCLK_DIV 5 |
| 40 | |
| 41 | |
| 42 | /* |
| 43 | * Memory Settings |
| 44 | */ |
| 45 | /* This board has a 64meg MT48H32M16 */ |
| 46 | #define CONFIG_MEM_ADD_WDTH 10 |
| 47 | #define CONFIG_MEM_SIZE 64 |
| 48 | |
| 49 | #define CONFIG_EBIU_SDRRC_VAL 0x0096 |
| 50 | #define CONFIG_EBIU_SDGCTL_VAL (SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS) |
| 51 | |
| 52 | #define CONFIG_EBIU_AMGCTL_VAL (AMCKEN | AMBEN_ALL) |
| 53 | #define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL) |
| 54 | #define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL) |
| 55 | |
Mike Frysinger | 912da8d | 2010-01-08 06:14:13 -0500 | [diff] [blame] | 56 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
Mike Frysinger | 84a9dda | 2008-10-12 21:32:52 -0400 | [diff] [blame] | 57 | #define CONFIG_SYS_MALLOC_LEN (384 * 1024) |
| 58 | |
| 59 | |
| 60 | /* |
| 61 | * Network Settings |
| 62 | */ |
| 63 | #if !defined(__ADSPBF512__) && !defined(__ADSPBF514__) |
| 64 | #define ADI_CMDS_NETWORK 1 |
| 65 | #define CONFIG_BFIN_MAC |
Mike Frysinger | 0c92942 | 2009-05-29 18:00:16 -0400 | [diff] [blame] | 66 | #define CONFIG_BFIN_MAC_PINS \ |
| 67 | { \ |
| 68 | P_MII0_ETxD0, \ |
| 69 | P_MII0_ETxD1, \ |
| 70 | P_MII0_ETxD2, \ |
| 71 | P_MII0_ETxD3, \ |
| 72 | P_MII0_ETxEN, \ |
| 73 | P_MII0_TxCLK, \ |
| 74 | P_MII0_PHYINT, \ |
| 75 | P_MII0_COL, \ |
| 76 | P_MII0_ERxD0, \ |
| 77 | P_MII0_ERxD1, \ |
| 78 | P_MII0_ERxD2, \ |
| 79 | P_MII0_ERxD3, \ |
| 80 | P_MII0_ERxDV, \ |
| 81 | P_MII0_ERxCLK, \ |
| 82 | P_MII0_CRS, \ |
| 83 | P_MII0_MDC, \ |
| 84 | P_MII0_MDIO, \ |
| 85 | 0 } |
Mike Frysinger | 84a9dda | 2008-10-12 21:32:52 -0400 | [diff] [blame] | 86 | #define CONFIG_NETCONSOLE 1 |
Mike Frysinger | 84a9dda | 2008-10-12 21:32:52 -0400 | [diff] [blame] | 87 | #endif |
| 88 | #define CONFIG_HOSTNAME bf518f-ezbrd |
| 89 | #define CONFIG_PHY_ADDR 3 |
Masahiro Yamada | c42f56d | 2014-04-18 19:09:49 +0900 | [diff] [blame] | 90 | #define CONFIG_LIB_RAND |
Mike Frysinger | 84a9dda | 2008-10-12 21:32:52 -0400 | [diff] [blame] | 91 | |
| 92 | /* |
| 93 | * Flash Settings |
| 94 | */ |
| 95 | #define CONFIG_FLASH_CFI_DRIVER |
| 96 | #define CONFIG_SYS_FLASH_BASE 0x20000000 |
| 97 | #define CONFIG_SYS_FLASH_CFI |
| 98 | #define CONFIG_SYS_FLASH_PROTECTION |
| 99 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 100 | #define CONFIG_SYS_MAX_FLASH_SECT 71 |
| 101 | |
| 102 | |
| 103 | /* |
| 104 | * SPI Settings |
| 105 | */ |
| 106 | #define CONFIG_BFIN_SPI |
| 107 | #define CONFIG_ENV_SPI_MAX_HZ 30000000 |
Mike Frysinger | afac8b0 | 2009-06-14 22:29:35 -0400 | [diff] [blame] | 108 | #define CONFIG_SF_DEFAULT_SPEED 30000000 |
Mike Frysinger | 84a9dda | 2008-10-12 21:32:52 -0400 | [diff] [blame] | 109 | #define CONFIG_SPI_FLASH |
Mike Frysinger | f52efca | 2009-05-29 17:02:37 -0400 | [diff] [blame] | 110 | #define CONFIG_SPI_FLASH_SST |
Mike Frysinger | 84a9dda | 2008-10-12 21:32:52 -0400 | [diff] [blame] | 111 | #define CONFIG_SPI_FLASH_STMICRO |
| 112 | |
| 113 | |
| 114 | /* |
| 115 | * Env Storage Settings |
| 116 | */ |
| 117 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) |
| 118 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
| 119 | #define CONFIG_ENV_OFFSET 0x10000 |
| 120 | #define CONFIG_ENV_SIZE 0x2000 |
| 121 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
| 122 | #else |
| 123 | #define CONFIG_ENV_IS_IN_FLASH |
| 124 | #define CONFIG_ENV_OFFSET 0x4000 |
| 125 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) |
| 126 | #define CONFIG_ENV_SIZE 0x2000 |
| 127 | #define CONFIG_ENV_SECT_SIZE 0x2000 |
| 128 | #endif |
Mike Frysinger | 76d8218 | 2009-07-21 22:17:36 -0400 | [diff] [blame] | 129 | #define CONFIG_ENV_IS_EMBEDDED_IN_LDR |
Mike Frysinger | 84a9dda | 2008-10-12 21:32:52 -0400 | [diff] [blame] | 130 | |
| 131 | |
| 132 | /* |
| 133 | * I2C Settings |
| 134 | */ |
Scott Jiang | c469703 | 2014-11-13 15:30:55 +0800 | [diff] [blame] | 135 | #define CONFIG_SYS_I2C |
Scott Jiang | fea9b69 | 2014-11-13 15:30:53 +0800 | [diff] [blame] | 136 | #define CONFIG_SYS_I2C_ADI |
Mike Frysinger | 84a9dda | 2008-10-12 21:32:52 -0400 | [diff] [blame] | 137 | |
| 138 | |
| 139 | /* |
| 140 | * SDH Settings |
| 141 | */ |
| 142 | #if !defined(__ADSPBF512__) |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 143 | #define CONFIG_GENERIC_MMC |
Mike Frysinger | 84a9dda | 2008-10-12 21:32:52 -0400 | [diff] [blame] | 144 | #define CONFIG_MMC |
| 145 | #define CONFIG_BFIN_SDH |
| 146 | #endif |
| 147 | |
| 148 | |
| 149 | /* |
| 150 | * Misc Settings |
| 151 | */ |
Graf Yang | ab68790 | 2009-05-24 02:34:34 -0400 | [diff] [blame] | 152 | #define CONFIG_BOARD_EARLY_INIT_F |
Mike Frysinger | 84a9dda | 2008-10-12 21:32:52 -0400 | [diff] [blame] | 153 | #define CONFIG_MISC_INIT_R |
| 154 | #define CONFIG_RTC_BFIN |
| 155 | #define CONFIG_UART_CONSOLE 0 |
Mike Frysinger | 84a9dda | 2008-10-12 21:32:52 -0400 | [diff] [blame] | 156 | |
| 157 | /* |
| 158 | * Pull in common ADI header for remaining command/environment setup |
| 159 | */ |
| 160 | #include <configs/bfin_adi_common.h> |
| 161 | |
Mike Frysinger | 84a9dda | 2008-10-12 21:32:52 -0400 | [diff] [blame] | 162 | #endif |