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wdenkbf9e3b32004-02-12 00:47:09 +00001/*
2 * Configuation settings for the Motorola MC5282EVB board.
3 *
4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenkbf9e3b32004-02-12 00:47:09 +00007 */
8
9/*
10 * board/config.h - configuration options, board specific
11 */
12
wdenk4e5ca3e2003-12-08 01:34:36 +000013#ifndef _CONFIG_M5282EVB_H
14#define _CONFIG_M5282EVB_H
15
wdenkbf9e3b32004-02-12 00:47:09 +000016/*
17 * High Level Configuration Options
18 * (easy to change)
19 */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050020#define CONFIG_MCFTMR
wdenk4e5ca3e2003-12-08 01:34:36 +000021
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050022#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020023#define CONFIG_SYS_UART_PORT (0)
TsiChung Liew79e07992008-08-15 16:50:07 +000024#define CONFIG_BAUDRATE 115200
wdenkbf9e3b32004-02-12 00:47:09 +000025
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050026#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
wdenkbf9e3b32004-02-12 00:47:09 +000027
28/* Configuration for environment
29 * Environment is embedded in u-boot in the second sector of the flash
30 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020031#define CONFIG_ENV_ADDR 0xffe04000
32#define CONFIG_ENV_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020033#define CONFIG_ENV_IS_IN_FLASH 1
wdenkbf9e3b32004-02-12 00:47:09 +000034
angelo@sysam.it5296cb12015-03-29 22:54:16 +020035#define LDS_BOARD_TEXT \
36 . = DEFINED(env_offset) ? env_offset : .; \
37 common/env_embedded.o (.text*);
38
Jon Loeliger8353e132007-07-08 14:14:17 -050039/*
Jon Loeliger659e2f62007-07-10 09:10:49 -050040 * BOOTP options
41 */
42#define CONFIG_BOOTP_BOOTFILESIZE
43#define CONFIG_BOOTP_BOOTPATH
44#define CONFIG_BOOTP_GATEWAY
45#define CONFIG_BOOTP_HOSTNAME
46
Jon Loeliger659e2f62007-07-10 09:10:49 -050047/*
Jon Loeliger8353e132007-07-08 14:14:17 -050048 * Command line configuration.
49 */
50#include <config_cmd_default.h>
TsiChung Liewdd9f0542010-03-11 22:12:53 -060051#define CONFIG_CMD_CACHE
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050052#define CONFIG_CMD_NET
53#define CONFIG_CMD_PING
54#define CONFIG_CMD_MII
wdenkbf9e3b32004-02-12 00:47:09 +000055
Jon Loeliger8353e132007-07-08 14:14:17 -050056#undef CONFIG_CMD_LOADS
57#undef CONFIG_CMD_LOADB
58
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050059#define CONFIG_MCFFEC
60#ifdef CONFIG_MCFFEC
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050061# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050062# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063# define CONFIG_SYS_DISCOVER_PHY
64# define CONFIG_SYS_RX_ETH_BUFFER 8
65# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050066
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067# define CONFIG_SYS_FEC0_PINMUX 0
68# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denk53677ef2008-05-20 16:00:29 +020069# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
71# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050072# define FECDUPLEX FULL
73# define FECSPEED _100BASET
74# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
76# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050077# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050079#endif
Jon Loeliger8353e132007-07-08 14:14:17 -050080
wdenkbf9e3b32004-02-12 00:47:09 +000081#define CONFIG_BOOTDELAY 5
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050082#ifdef CONFIG_MCFFEC
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050083# define CONFIG_IPADDR 192.162.1.2
84# define CONFIG_NETMASK 255.255.255.0
85# define CONFIG_SERVERIP 192.162.1.1
86# define CONFIG_GATEWAYIP 192.162.1.1
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050087#endif /* CONFIG_MCFFEC */
88
TsiChung Liew4cb4e652008-08-11 15:54:25 +000089#define CONFIG_HOSTNAME M5282EVB
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050090#define CONFIG_EXTRA_ENV_SETTINGS \
91 "netdev=eth0\0" \
92 "loadaddr=10000\0" \
93 "u-boot=u-boot.bin\0" \
94 "load=tftp ${loadaddr) ${u-boot}\0" \
95 "upd=run load; run prog\0" \
96 "prog=prot off ffe00000 ffe3ffff;" \
97 "era ffe00000 ffe3ffff;" \
98 "cp.b ${loadaddr} ffe00000 ${filesize};"\
99 "save\0" \
100 ""
wdenkbf9e3b32004-02-12 00:47:09 +0000101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_PROMPT "-> "
103#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkbf9e3b32004-02-12 00:47:09 +0000104
Jon Loeliger8353e132007-07-08 14:14:17 -0500105#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkbf9e3b32004-02-12 00:47:09 +0000107#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkbf9e3b32004-02-12 00:47:09 +0000109#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
111#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
112#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkbf9e3b32004-02-12 00:47:09 +0000113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_LOAD_ADDR 0x20000
wdenkbf9e3b32004-02-12 00:47:09 +0000115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_MEMTEST_START 0x400
117#define CONFIG_SYS_MEMTEST_END 0x380000
wdenkbf9e3b32004-02-12 00:47:09 +0000118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_CLK 64000000
wdenkbf9e3b32004-02-12 00:47:09 +0000120
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500121/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
124#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
wdenkbf9e3b32004-02-12 00:47:09 +0000125
126/*
127 * Low Level Configuration Settings
128 * (address mappings, register initial values, etc.)
129 * You should know what you are doing if you make changes here.
130 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_MBAR 0x40000000
wdenkbf9e3b32004-02-12 00:47:09 +0000132
wdenkbf9e3b32004-02-12 00:47:09 +0000133/*-----------------------------------------------------------------------
134 * Definitions for initial stack pointer and data area (in DPRAM)
135 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200137#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200138#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkbf9e3b32004-02-12 00:47:09 +0000140
141/*-----------------------------------------------------------------------
142 * Start addresses for the final memory configuration
143 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkbf9e3b32004-02-12 00:47:09 +0000145 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_SDRAM_BASE 0x00000000
147#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
TsiChung Liew012522f2008-10-21 10:03:07 +0000148#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
150#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
wdenkbf9e3b32004-02-12 00:47:09 +0000151
152/* If M5282 port is fully implemented the monitor base will be behind
153 * the vector table. */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200154#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500156#else
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200157#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500158#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_MONITOR_LEN 0x20000
161#define CONFIG_SYS_MALLOC_LEN (256 << 10)
162#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
wdenkbf9e3b32004-02-12 00:47:09 +0000163
wdenkbf9e3b32004-02-12 00:47:09 +0000164/*
165 * For booting Linux, the board info and command line data
166 * have to be in the first 8 MB of memory, since this is
167 * the maximum mapped by the Linux kernel during initialization ??
168 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
wdenkbf9e3b32004-02-12 00:47:09 +0000170
171/*-----------------------------------------------------------------------
172 * FLASH organization
173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_FLASH_CFI
175#ifdef CONFIG_SYS_FLASH_CFI
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500176
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200177# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
179# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
180# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
181# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
182# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
183# define CONFIG_SYS_FLASH_CHECKSUM
184# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500185#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000186
187/*-----------------------------------------------------------------------
188 * Cache Configuration
189 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_CACHELINE_SIZE 16
wdenkbf9e3b32004-02-12 00:47:09 +0000191
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600192#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200193 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600194#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200195 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600196#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
197#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
198 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
199 CF_ACR_EN | CF_ACR_SM_ALL)
200#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
201 CF_CACR_CEIB | CF_CACR_DBWE | \
202 CF_CACR_EUSP)
203
wdenkbf9e3b32004-02-12 00:47:09 +0000204/*-----------------------------------------------------------------------
205 * Memory bank definitions
206 */
TsiChung Liew012522f2008-10-21 10:03:07 +0000207#define CONFIG_SYS_CS0_BASE 0xFFE00000
208#define CONFIG_SYS_CS0_CTRL 0x00001980
209#define CONFIG_SYS_CS0_MASK 0x001F0001
210
wdenkbf9e3b32004-02-12 00:47:09 +0000211/*-----------------------------------------------------------------------
212 * Port configuration
213 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
215#define CONFIG_SYS_PADDR 0x0000000
216#define CONFIG_SYS_PADAT 0x0000000
wdenkbf9e3b32004-02-12 00:47:09 +0000217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
219#define CONFIG_SYS_PBDDR 0x0000000
220#define CONFIG_SYS_PBDAT 0x0000000
wdenk4e5ca3e2003-12-08 01:34:36 +0000221
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
223#define CONFIG_SYS_PCDDR 0x0000000
224#define CONFIG_SYS_PCDAT 0x0000000
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
227#define CONFIG_SYS_PCDDR 0x0000000
228#define CONFIG_SYS_PCDAT 0x0000000
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_PEHLPAR 0xC0
231#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
232#define CONFIG_SYS_DDRUA 0x05
233#define CONFIG_SYS_PJPAR 0xFF
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500234
235#endif /* _CONFIG_M5282EVB_H */