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TsiChungLiewa1436a82007-08-16 13:20:50 -05001/*
2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
3 * Hayden Fraser (Hayden.Fraser@freescale.com)
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiewa1436a82007-08-16 13:20:50 -05006 */
7
8#ifndef _M5253EVBE_H
9#define _M5253EVBE_H
10
TsiChungLiewa1436a82007-08-16 13:20:50 -050011#define CONFIG_M5253EVBE /* define board type */
12
13#define CONFIG_MCFTMR
14
15#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020016#define CONFIG_SYS_UART_PORT (0)
TsiChung Liew80ba61f2008-08-06 14:17:09 -050017#define CONFIG_BAUDRATE 115200
TsiChungLiewa1436a82007-08-16 13:20:50 -050018
19#undef CONFIG_WATCHDOG /* disable watchdog */
20
21#define CONFIG_BOOTDELAY 5
22
23/* Configuration for environment
24 * Environment is embedded in u-boot in the second sector of the flash
25 */
26#ifndef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020027#define CONFIG_ENV_OFFSET 0x4000
28#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020029#define CONFIG_ENV_IS_IN_FLASH 1
TsiChungLiewa1436a82007-08-16 13:20:50 -050030#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020031#define CONFIG_ENV_ADDR 0xffe04000
32#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020033#define CONFIG_ENV_IS_IN_FLASH 1
TsiChungLiewa1436a82007-08-16 13:20:50 -050034#endif
35
angelo@sysam.it5296cb12015-03-29 22:54:16 +020036#define LDS_BOARD_TEXT \
37 . = DEFINED(env_offset) ? env_offset : .; \
38 common/env_embedded.o (.text)
39
40
TsiChungLiewa1436a82007-08-16 13:20:50 -050041/*
42 * BOOTP options
43 */
44#undef CONFIG_BOOTP_BOOTFILESIZE
45#undef CONFIG_BOOTP_BOOTPATH
46#undef CONFIG_BOOTP_GATEWAY
47#undef CONFIG_BOOTP_HOSTNAME
48
49/*
50 * Command line configuration.
51 */
52#include <config_cmd_default.h>
TsiChung Liewdd9f0542010-03-11 22:12:53 -060053#define CONFIG_CMD_CACHE
TsiChungLiewa1436a82007-08-16 13:20:50 -050054#undef CONFIG_CMD_NET
55#define CONFIG_CMD_LOADB
56#define CONFIG_CMD_LOADS
57#define CONFIG_CMD_EXT2
58#define CONFIG_CMD_FAT
59#define CONFIG_CMD_IDE
60#define CONFIG_CMD_MEMORY
61#define CONFIG_CMD_MISC
62
63/* ATA */
64#define CONFIG_DOS_PARTITION
65#define CONFIG_MAC_PARTITION
66#define CONFIG_IDE_RESET 1
67#define CONFIG_IDE_PREINIT 1
68#define CONFIG_ATAPI
69#undef CONFIG_LBA48
70
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_IDE_MAXBUS 1
72#define CONFIG_SYS_IDE_MAXDEVICE 2
TsiChungLiewa1436a82007-08-16 13:20:50 -050073
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
75#define CONFIG_SYS_ATA_IDE0_OFFSET 0
TsiChungLiewa1436a82007-08-16 13:20:50 -050076
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
78#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
79#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
80#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
TsiChungLiewa1436a82007-08-16 13:20:50 -050081
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChungLiewa1436a82007-08-16 13:20:50 -050083
84#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChungLiewa1436a82007-08-16 13:20:50 -050086#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChungLiewa1436a82007-08-16 13:20:50 -050088#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
90#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
91#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
TsiChungLiewa1436a82007-08-16 13:20:50 -050092
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_LOAD_ADDR 0x00100000
TsiChungLiewa1436a82007-08-16 13:20:50 -050094
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_MEMTEST_START 0x400
96#define CONFIG_SYS_MEMTEST_END 0x380000
TsiChungLiewa1436a82007-08-16 13:20:50 -050097
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
99#define CONFIG_SYS_FAST_CLK
100#ifdef CONFIG_SYS_FAST_CLK
101# define CONFIG_SYS_PLLCR 0x1243E054
102# define CONFIG_SYS_CLK 140000000
TsiChungLiewa1436a82007-08-16 13:20:50 -0500103#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104# define CONFIG_SYS_PLLCR 0x135a4140
105# define CONFIG_SYS_CLK 70000000
TsiChungLiewa1436a82007-08-16 13:20:50 -0500106#endif
107
108/*
109 * Low Level Configuration Settings
110 * (address mappings, register initial values, etc.)
111 * You should know what you are doing if you make changes here.
112 */
113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
115#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
TsiChungLiewa1436a82007-08-16 13:20:50 -0500116
117/*
118 * Definitions for initial stack pointer and data area (in DPRAM)
119 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200121#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200122#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChungLiewa1436a82007-08-16 13:20:50 -0500124
125/*
126 * Start addresses for the final memory configuration
127 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChungLiewa1436a82007-08-16 13:20:50 -0500129 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_SDRAM_BASE 0x00000000
131#define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */
TsiChungLiewa1436a82007-08-16 13:20:50 -0500132
133#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_MONITOR_BASE 0x20000
TsiChungLiewa1436a82007-08-16 13:20:50 -0500135#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
TsiChungLiewa1436a82007-08-16 13:20:50 -0500137#endif
138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_MONITOR_LEN 0x40000
140#define CONFIG_SYS_MALLOC_LEN (256 << 10)
141#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
TsiChungLiewa1436a82007-08-16 13:20:50 -0500142
143/*
144 * For booting Linux, the board info and command line data
145 * have to be in the first 8 MB of memory, since this is
146 * the maximum mapped by the Linux kernel during initialization ??
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liewd6e4baf2009-01-27 12:57:47 +0000149#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChungLiewa1436a82007-08-16 13:20:50 -0500150
151/* FLASH organization */
TsiChung Liew012522f2008-10-21 10:03:07 +0000152#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
154#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
155#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
TsiChungLiewa1436a82007-08-16 13:20:50 -0500156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200158#define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_FLASH_SIZE 0x200000
160#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
TsiChungLiewa1436a82007-08-16 13:20:50 -0500161
162/* Cache Configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChungLiewa1436a82007-08-16 13:20:50 -0500164
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600165#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200166 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600167#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200168 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600169#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
170#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
171 CF_ADDRMASK(2) | \
172 CF_ACR_EN | CF_ACR_SM_ALL)
173#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
174 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
175 CF_ACR_EN | CF_ACR_SM_ALL)
176#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
177 CF_CACR_DBWE)
178
TsiChungLiewa1436a82007-08-16 13:20:50 -0500179/* Port configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_FECI2C 0xF0
TsiChungLiewa1436a82007-08-16 13:20:50 -0500181
TsiChung Liew012522f2008-10-21 10:03:07 +0000182#define CONFIG_SYS_CS0_BASE 0xFFE00000
183#define CONFIG_SYS_CS0_MASK 0x001F0021
184#define CONFIG_SYS_CS0_CTRL 0x00001D80
TsiChungLiewa1436a82007-08-16 13:20:50 -0500185
186/*-----------------------------------------------------------------------
187 * Port configuration
188 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
190#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
191#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
192#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
193#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
194#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
195#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
TsiChungLiewa1436a82007-08-16 13:20:50 -0500196
197#endif /* _M5253EVB_H */