Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007-2008 |
| 3 | * Stelian Pop <stelian.pop@leadtechdesign.com> |
| 4 | * Lead Tech Design <www.leadtechdesign.com> |
| 5 | * Ilko Iliev <www.ronetix.at> |
| 6 | * |
| 7 | * (C) Copyright 2009 |
| 8 | * Eric Benard <eric@eukrea.com> |
| 9 | * |
| 10 | * See file CREDITS for list of people who contributed to this |
| 11 | * project. |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or |
| 14 | * modify it under the terms of the GNU General Public License as |
| 15 | * published by the Free Software Foundation; either version 2 of |
| 16 | * the License, or (at your option) any later version. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License |
| 24 | * along with this program; if not, write to the Free Software |
| 25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 26 | * MA 02111-1307 USA |
| 27 | */ |
| 28 | |
| 29 | #include <common.h> |
| 30 | #include <asm/sizes.h> |
| 31 | #include <asm/arch/at91sam9260.h> |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 32 | #include <asm/arch/at91sam9_smc.h> |
| 33 | #include <asm/arch/at91_common.h> |
| 34 | #include <asm/arch/at91_pmc.h> |
| 35 | #include <asm/arch/at91_rstc.h> |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 36 | #include <asm/arch/at91_matrix.h> |
| 37 | #include <asm/arch/at91_pio.h> |
| 38 | #include <asm/arch/clk.h> |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 39 | #include <asm/arch/io.h> |
| 40 | #include <asm/arch/hardware.h> |
| 41 | #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) |
| 42 | #include <net.h> |
| 43 | #endif |
| 44 | #include <netdev.h> |
| 45 | |
| 46 | DECLARE_GLOBAL_DATA_PTR; |
| 47 | |
| 48 | /* ------------------------------------------------------------------------- */ |
| 49 | /* |
| 50 | * Miscelaneous platform dependent initialisations |
| 51 | */ |
| 52 | |
| 53 | #ifdef CONFIG_CMD_NAND |
| 54 | static void cpu9260_nand_hw_init(void) |
| 55 | { |
| 56 | unsigned long csa; |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 57 | at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE; |
| 58 | at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; |
| 59 | at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 60 | |
| 61 | /* Enable CS3 */ |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 62 | csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A; |
| 63 | writel(csa, &matrix->csa); |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 64 | |
| 65 | /* Configure SMC CS3 for NAND/SmartMedia */ |
| 66 | #if defined(CONFIG_CPU9G20) |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 67 | writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | |
| 68 | AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), |
| 69 | &smc->cs[3].setup); |
| 70 | writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | |
| 71 | AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), |
| 72 | &smc->cs[3].pulse); |
| 73 | writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), |
| 74 | &smc->cs[3].cycle); |
| 75 | writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | |
| 76 | AT91_SMC_MODE_EXNW_DISABLE | |
| 77 | AT91_SMC_MODE_DBW_8 | |
| 78 | AT91_SMC_MODE_TDF_CYCLE(3), |
| 79 | &smc->cs[3].mode); |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 80 | #elif defined(CONFIG_CPU9260) |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 81 | writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | |
| 82 | AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), |
| 83 | &smc->cs[3].setup); |
| 84 | writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | |
| 85 | AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), |
| 86 | &smc->cs[3].pulse); |
| 87 | writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), |
| 88 | &smc->cs[3].cycle); |
| 89 | writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | |
| 90 | AT91_SMC_MODE_EXNW_DISABLE | |
| 91 | AT91_SMC_MODE_DBW_8 | |
| 92 | AT91_SMC_MODE_TDF_CYCLE(2), |
| 93 | &smc->cs[3].mode); |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 94 | #endif |
| 95 | |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 96 | writel(1 << AT91SAM9260_ID_PIOC, &pmc->pcer); |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 97 | |
| 98 | /* Configure RDY/BSY */ |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 99 | at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 100 | |
| 101 | /* Enable NandFlash */ |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 102 | at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 103 | } |
| 104 | #endif |
| 105 | |
| 106 | #ifdef CONFIG_MACB |
| 107 | static void cpu9260_macb_hw_init(void) |
| 108 | { |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 109 | unsigned long rstcmr; |
| 110 | at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; |
| 111 | at91_rstc_t *rstc = (at91_rstc_t *) AT91_RSTC_BASE; |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 112 | |
| 113 | /* Enable clock */ |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 114 | writel(1 << AT91SAM9260_ID_EMAC, &pmc->pcer); |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 115 | |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 116 | at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1); |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 117 | |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 118 | rstcmr = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 119 | |
| 120 | /* Need to reset PHY -> 500ms reset */ |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 121 | writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0xD) | |
| 122 | AT91_RSTC_MR_URSTEN, &rstc->mr); |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 123 | |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 124 | writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 125 | |
| 126 | /* Wait for end hardware reset */ |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 127 | while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 128 | ; |
| 129 | |
| 130 | /* Restore NRST value */ |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 131 | writel(AT91_RSTC_KEY | rstcmr | AT91_RSTC_MR_URSTEN, &rstc->mr); |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 132 | |
| 133 | at91_macb_hw_init(); |
| 134 | } |
| 135 | #endif |
| 136 | |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 137 | int board_early_init_f(void) |
| 138 | { |
| 139 | at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; |
| 140 | |
| 141 | writel((1 << AT91SAM9260_ID_PIOA) | |
| 142 | (1 << AT91SAM9260_ID_PIOC) | |
| 143 | (1 << AT91SAM9260_ID_PIOB), |
| 144 | &pmc->pcer); |
| 145 | |
| 146 | at91_serial_hw_init(); |
| 147 | |
| 148 | return 0; |
| 149 | } |
| 150 | |
| 151 | |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 152 | int board_init(void) |
| 153 | { |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 154 | /* arch number of the board */ |
| 155 | #if defined(CONFIG_CPU9G20) |
Eric Benard | 94d50c5 | 2009-10-12 10:08:20 +0200 | [diff] [blame] | 156 | gd->bd->bi_arch_number = MACH_TYPE_CPUAT9G20; |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 157 | #elif defined(CONFIG_CPU9260) |
| 158 | gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260; |
| 159 | #endif |
| 160 | |
| 161 | /* adress of boot parameters */ |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 162 | gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 163 | |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 164 | #ifdef CONFIG_CMD_NAND |
| 165 | cpu9260_nand_hw_init(); |
| 166 | #endif |
| 167 | #ifdef CONFIG_MACB |
| 168 | cpu9260_macb_hw_init(); |
| 169 | #endif |
| 170 | #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) |
| 171 | status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); |
| 172 | #endif |
| 173 | return 0; |
| 174 | } |
| 175 | |
| 176 | int dram_init(void) |
| 177 | { |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 178 | gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE, |
| 179 | CONFIG_SYS_SDRAM_SIZE); |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 180 | return 0; |
| 181 | } |
| 182 | |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 183 | int board_eth_init(bd_t *bis) |
| 184 | { |
| 185 | int rc = 0; |
| 186 | #ifdef CONFIG_MACB |
Eric Benard | c2b2a07 | 2011-04-03 06:35:54 +0000 | [diff] [blame^] | 187 | rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0); |
Tom Rix | 23b8098 | 2009-09-27 11:10:09 -0500 | [diff] [blame] | 188 | #endif |
| 189 | return rc; |
| 190 | } |