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wdenkda93ed82004-09-29 11:02:56 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2003-2005
wdenkda93ed82004-09-29 11:02:56 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 * changes for 16M board
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/*
33 * High Level Configuration Options
34 * (easy to change)
35 */
36
37#undef CONFIG_MPC860
38#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
39#define CONFIG_RPXLITE 1 /* QUANTUM is the RPXlite clone */
40#define CONFIG_RMU 1 /* The QUNATUM is based on our RMU */
41
42#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
43#undef CONFIG_8xx_CONS_SMC2
44#undef CONFIG_8xx_CONS_NONE
45#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
46#if 0
47#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
48#else
49#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
50#endif
51
52/* default developmenmt environment */
53
wdenkda93ed82004-09-29 11:02:56 +000054#define CONFIG_ETHADDR 00:0B:17:00:00:00
55
56#define CONFIG_IPADDR 10.10.69.10
57#define CONFIG_SERVERIP 10.10.69.49
58#define CONFIG_NETMASK 255.255.255.0
59#define CONFIG_HOSTNAME QUANTUM
60#define CONFIG_ROOTPATH /opt/eldk/pcc_8xx
61
62#define CONFIG_BOOTARGS "root=/dev/ram rw"
63
64#define CONFIG_BOOTCOMMAND "bootm ff000000"
65
66#define CONFIG_EXTRA_ENV_SETTINGS \
67 "serial#=12345\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010068 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
wdenkda93ed82004-09-29 11:02:56 +000069 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010070 "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0"
wdenkda93ed82004-09-29 11:02:56 +000071
72/*
73 * Select the more full-featured memory test (Barr embedded systems)
74 */
75#define CFG_ALT_MEMTEST
76
77#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
78#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
79
80
81/* M48T02 Paralled access timekeeper with same interface as the M48T35A*/
82#define CONFIG_RTC_M48T35A 1
83
84#if 0
85#define CONFIG_WATCHDOG 1 /* watchdog enabled */
86#else
87#undef CONFIG_WATCHDOG
88#endif
89
90/* NVRAM and RTC */
91#define CFG_NVRAM_BASE_ADDR 0xFA000000
92#define CFG_NVRAM_SIZE 2048
93
94
Jon Loeliger90cc3eb2007-07-04 22:33:23 -050095/*
96 * Command line configuration.
97 */
98#include <config_cmd_default.h>
99
100#define CONFIG_CMD_DATE
101#define CONFIG_CMD_DHCP
102#define CONFIG_CMD_NFS
103#define CONFIG_CMD_PING
104#define CONFIG_CMD_REGINFO
105#define CONFIG_CMD_SNTP
106
wdenkda93ed82004-09-29 11:02:56 +0000107
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500108/*
109 * BOOTP options
110 */
111#define CONFIG_BOOTP_SUBNETMASK
112#define CONFIG_BOOTP_GATEWAY
113#define CONFIG_BOOTP_HOSTNAME
114#define CONFIG_BOOTP_BOOTPATH
115#define CONFIG_BOOTP_BOOTFILESIZE
116
wdenkda93ed82004-09-29 11:02:56 +0000117
wdenkda93ed82004-09-29 11:02:56 +0000118#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
Wolfgang Denkc37207d2008-07-16 16:38:59 +0200119#define CONFIG_AUTOBOOT_PROMPT \
120 "\nEnter password - autoboot in %d sec...\n", bootdelay
wdenkda93ed82004-09-29 11:02:56 +0000121#define CONFIG_AUTOBOOT_DELAY_STR "system"
122/*
123 * Miscellaneous configurable options
124 */
125#define CFG_LONGHELP /* undef to save memory */
126#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500127#if defined(CONFIG_CMD_KGDB)
wdenkda93ed82004-09-29 11:02:56 +0000128#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
129#else
130#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
131#endif
132#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
133#define CFG_MAXARGS 16 /* max number of command args */
134#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
135
136#define CFG_MEMTEST_START 0x00040000 /* memtest works on */
137#define CFG_MEMTEST_END 0x01f00000 /* 256K ... 15 MB in DRAM */
138
139#define CFG_LOAD_ADDR 0x100000 /* default load address */
140
141#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
142
143#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
144
145/*
146 * Low Level Configuration Settings
147 * (address mappings, register initial values, etc.)
148 * You should know what you are doing if you make changes here.
149 */
150/*-----------------------------------------------------------------------
151 * Internal Memory Mapped Register
152 */
153#define CFG_IMMR 0xFA200000
154
155/*-----------------------------------------------------------------------
156 * Definitions for initial stack pointer and data area (in DPRAM)
157 */
158#define CFG_INIT_RAM_ADDR CFG_IMMR
159#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
160#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
161#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
162#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
163
164/*-----------------------------------------------------------------------
165 * Start addresses for the final memory configuration
166 * (Set up by the startup code)
167 * Please note that CFG_SDRAM_BASE _must_ start at 0
168 */
169#define CFG_SDRAM_BASE 0x00000000
170#define CFG_FLASH_BASE 0xFF000000
171
172#if 1
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200173 #define CONFIG_FLASH_CFI_DRIVER
wdenkda93ed82004-09-29 11:02:56 +0000174#else
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200175 #undef CONFIG_FLASH_CFI_DRIVER
wdenkda93ed82004-09-29 11:02:56 +0000176#endif
177
178
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200179#ifdef CONFIG_FLASH_CFI_DRIVER
wdenkda93ed82004-09-29 11:02:56 +0000180 #define CFG_FLASH_CFI 1
181 #undef CFG_FLASH_USE_BUFFER_WRITE
182 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
183#endif
184
185/*%%% #define CFG_FLASH_BASE 0xFFF00000 */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500186#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
wdenkda93ed82004-09-29 11:02:56 +0000187#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
188#else
189#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
190#endif
191#define CFG_MONITOR_BASE 0xFFF00000
192/*%%% #define CFG_MONITOR_BASE CFG_FLASH_BASE */
193#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
194
195/*
196 * For booting Linux, the board info and command line data
197 * have to be in the first 8 MB of memory, since this is
198 * the maximum mapped by the Linux kernel during initialization.
199 */
200#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
201
202/*-----------------------------------------------------------------------
203 * FLASH organization
204 */
205#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
206#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
207
208#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
209#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
210
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200211#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200212#define CONFIG_ENV_OFFSET 0x00F40000 /* Offset of Environment Sector absolute address 0xfff40000*/
213#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
214#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
215#define CONFIG_ENV_ADDR (CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
wdenkda93ed82004-09-29 11:02:56 +0000216
217/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200218#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
219#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkda93ed82004-09-29 11:02:56 +0000220
221/* FPGA */
222#define CONFIG_MISC_INIT_R
223#define CFG_FPGA_SPARTAN2
224#define CFG_FPGA_PROG_FEEDBACK
225
226
227/*-----------------------------------------------------------------------
228 * Reset address
229 */
230#define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
231
232/*-----------------------------------------------------------------------
233 * Cache Configuration
234 */
235#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500236#if defined(CONFIG_CMD_KGDB)
wdenkda93ed82004-09-29 11:02:56 +0000237#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
238#endif
239
240/*-----------------------------------------------------------------------
241 * SYPCR - System Protection Control 11-9
242 * SYPCR can only be written once after reset!
243 *-----------------------------------------------------------------------
244 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
245 */
246#if defined(CONFIG_WATCHDOG)
247#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
248 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
249#else
250#define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
251#endif
252
253/*-----------------------------------------------------------------------
254 * SIUMCR - SIU Module Configuration 11-6
255 *-----------------------------------------------------------------------
256 * PCMCIA config., multi-function pin tri-state
257 */
258#define CFG_SIUMCR (SIUMCR_MLRC10)
259
260/*-----------------------------------------------------------------------
261 * TBSCR - Time Base Status and Control 11-26
262 *-----------------------------------------------------------------------
263 * Clear Reference Interrupt Status, Timebase freezing enabled
264 */
265#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
266
267/*-----------------------------------------------------------------------
268 * RTCSC - Real-Time Clock Status and Control Register 11-27
269 *-----------------------------------------------------------------------
270 */
271/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
272#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE)
273
274/*-----------------------------------------------------------------------
275 * PISCR - Periodic Interrupt Status and Control 11-31
276 *-----------------------------------------------------------------------
277 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
278 */
279#define CFG_PISCR (PISCR_PS | PISCR_PITF)
280
281/*-----------------------------------------------------------------------
282 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
283 *-----------------------------------------------------------------------
284 * Reset PLL lock status sticky bit, timer expired status bit and timer
285 * interrupt status bit
286 *
287 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
288 */
289/* up to 50 MHz we use a 1:1 clock */
290#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
291
292/*-----------------------------------------------------------------------
293 * SCCR - System Clock and reset Control Register 15-27
294 *-----------------------------------------------------------------------
295 * Set clock output, timebase and RTC source and divider,
296 * power management and some other internal clocks
297 */
298#define SCCR_MASK SCCR_EBDF00
299/* up to 50 MHz we use a 1:1 clock */
300#define CFG_SCCR (SCCR_COM00 | SCCR_TBS)
301
302/*-----------------------------------------------------------------------
303 * PCMCIA stuff
304 *-----------------------------------------------------------------------
305 *
306 */
307#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
308#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
309#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
310#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
311#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
312#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
313#define CFG_PCMCIA_IO_ADDR (0xEC000000)
314#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
315
316/*-----------------------------------------------------------------------
317 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
318 *-----------------------------------------------------------------------
319 */
320
321#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
322
323#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
324#undef CONFIG_IDE_LED /* LED for ide not supported */
325#undef CONFIG_IDE_RESET /* reset for ide not supported */
326
327#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
328#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
329
330#define CFG_ATA_IDE0_OFFSET 0x0000
331
332#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
333
334/* Offset for data I/O */
335#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
336
337/* Offset for normal register accesses */
338#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
339
340/* Offset for alternate registers */
341#define CFG_ATA_ALT_OFFSET 0x0100
342
343/*-----------------------------------------------------------------------
344 *
345 *-----------------------------------------------------------------------
346 *
347 */
348/*#define CFG_DER 0x2002000F*/
349#define CFG_DER 0
350
351/*
352 * Init Memory Controller:
353 *
354 * BR0 and OR0 (FLASH)
355 */
356
357#define FLASH_BASE_PRELIM 0xFE000000 /* FLASH base */
358#define CFG_PRELIM_OR_AM 0xFE000000 /* OR addr mask */
359
360/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
361#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
362
363#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
364#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
365
366/*
367 * BR1 and OR1 (SDRAM)
368 *
369 */
370#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
371#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */
372
373/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
374#define CFG_OR_TIMING_SDRAM 0x00000E00
375
376#define CFG_OR1_PRELIM (0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */
377#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
378
379/* RPXLITE mem setting */
380#define CFG_BR3_PRELIM 0xFA400001 /* FPGA */
381#define CFG_OR3_PRELIM 0xFFFF8910
382
383#define CFG_BR4_PRELIM 0xFA000401 /* NVRAM&SRAM */
384#define CFG_OR4_PRELIM 0xFFFE0970
385
386/*
387 * Memory Periodic Timer Prescaler
388 */
389
390/* periodic timer for refresh */
391#define CFG_MAMR_PTA 20
392
393/*
394 * Refresh clock Prescalar
395 */
396#define CFG_MPTPR MPTPR_PTP_DIV2
397
398/*
399 * MAMR settings for SDRAM
400 */
401
402/* 9 column SDRAM */
403#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
404 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
405 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
406
407/*
408 * Internal Definitions
409 *
410 * Boot Flags
411 */
412#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
413#define BOOTFLAG_WARM 0x02 /* Software reboot */
414
415/*
416 * BCSRx
417 *
418 * Board Status and Control Registers
419 *
420 */
421
422#define BCSR0 0xFA400000
423#define BCSR1 0xFA400001
424#define BCSR2 0xFA400002
425#define BCSR3 0xFA400003
426
427#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
428#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
429#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
430#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
431#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
432#define BCSR0_COLTEST 0x20
433#define BCSR0_ETHLPBK 0x40
434#define BCSR0_ETHEN 0x80
435
436#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
437#define BCSR1_PCVCTL6 0x02
438#define BCSR1_PCVCTL5 0x04
439#define BCSR1_PCVCTL4 0x08
440#define BCSR1_IPB5SEL 0x10
441
442#define BCSR2_ENPA5HDR 0x08 /* USB Control */
443#define BCSR2_ENUSBCLK 0x10
444#define BCSR2_USBPWREN 0x20
445#define BCSR2_USBSPD 0x40
446#define BCSR2_USBSUSP 0x80
447
448#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
449#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
450#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
451#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
452#define BCSR3_D27 0x10 /* Dip Switch settings */
453#define BCSR3_D26 0x20
454#define BCSR3_D25 0x40
455#define BCSR3_D24 0x80
456
457#endif /* __CONFIG_H */