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wdenkf12e5682003-07-07 20:07:54 +00001/*
Wolfgang Denk23c5d252014-10-24 15:31:26 +02002 * (C) Copyright 2000-2014
wdenkf12e5682003-07-07 20:07:54 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkf12e5682003-07-07 20:07:54 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
21#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */
Wolfgang Denk23c5d252014-10-24 15:31:26 +020022#define CONFIG_DISPLAY_BOARDINFO
wdenkf12e5682003-07-07 20:07:54 +000023
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0x40000000
25
wdenkf12e5682003-07-07 20:07:54 +000026#ifdef CONFIG_LCD /* with LCD controller ? */
Jeroen Hofstee59155f42013-01-22 10:44:09 +000027#define CONFIG_MPC8XX_LCD
wdenkfd3103b2003-11-25 16:55:19 +000028/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */
wdenkf12e5682003-07-07 20:07:54 +000029#endif
30
31#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020032#define CONFIG_SYS_SMC_RXBUFLEN 128
33#define CONFIG_SYS_MAXIDLE 10
wdenkf12e5682003-07-07 20:07:54 +000034#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
wdenkf12e5682003-07-07 20:07:54 +000035
wdenkae3af052003-08-07 22:18:11 +000036#define CONFIG_BOOTCOUNT_LIMIT
37
38#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf12e5682003-07-07 20:07:54 +000039
40#define CONFIG_BOARD_TYPES 1 /* support board types */
41
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010042#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenkf12e5682003-07-07 20:07:54 +000043
44#undef CONFIG_BOOTARGS
45
46#define CONFIG_EXTRA_ENV_SETTINGS \
47 "netdev=eth0\0" \
48 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010049 "nfsroot=${serverip}:${rootpath}\0" \
wdenkf12e5682003-07-07 20:07:54 +000050 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010051 "addip=setenv bootargs ${bootargs} " \
52 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
53 ":${hostname}:${netdev}:off panic=1\0" \
wdenkf12e5682003-07-07 20:07:54 +000054 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010055 "bootm ${kernel_addr}\0" \
wdenkf12e5682003-07-07 20:07:54 +000056 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010057 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
58 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkf12e5682003-07-07 20:07:54 +000059 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020060 "hostname=TQM823M\0" \
61 "bootfile=TQM823M/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020062 "fdt_addr=40080000\0" \
63 "kernel_addr=400A0000\0" \
64 "ramdisk_addr=40280000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020065 "u-boot=TQM823M/u-image.bin\0" \
66 "load=tftp 200000 ${u-boot}\0" \
67 "update=prot off 40000000 +${filesize};" \
68 "era 40000000 +${filesize};" \
69 "cp.b 200000 40000000 ${filesize};" \
70 "sete filesize;save\0" \
wdenkf12e5682003-07-07 20:07:54 +000071 ""
72#define CONFIG_BOOTCOMMAND "run flash_self"
73
74#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf12e5682003-07-07 20:07:54 +000076
77#undef CONFIG_WATCHDOG /* watchdog disabled */
78
79#ifdef CONFIG_LCD
80# undef CONFIG_STATUS_LED /* disturbs display */
81#else
82# define CONFIG_STATUS_LED 1 /* Status LED enabled */
83#endif /* CONFIG_LCD */
84
85#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
86
Jon Loeliger37d4bb72007-07-09 21:38:02 -050087/*
88 * BOOTP options
89 */
90#define CONFIG_BOOTP_SUBNETMASK
91#define CONFIG_BOOTP_GATEWAY
92#define CONFIG_BOOTP_HOSTNAME
93#define CONFIG_BOOTP_BOOTPATH
94#define CONFIG_BOOTP_BOOTFILESIZE
95
wdenkf12e5682003-07-07 20:07:54 +000096#define CONFIG_MAC_PARTITION
97#define CONFIG_DOS_PARTITION
98
99#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
100
Jon Loeliger26946902007-07-04 22:30:50 -0500101/*
102 * Command line configuration.
103 */
Jon Loeliger26946902007-07-04 22:30:50 -0500104#define CONFIG_CMD_DATE
Jon Loeliger26946902007-07-04 22:30:50 -0500105#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200106#define CONFIG_CMD_JFFS2
wdenkf12e5682003-07-07 20:07:54 +0000107
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200108#define CONFIG_NETCONSOLE
109
wdenkf12e5682003-07-07 20:07:54 +0000110/*
111 * Miscellaneous configurable options
112 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkf12e5682003-07-07 20:07:54 +0000114
Wolfgang Denk2751a952006-10-28 02:29:14 +0200115#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
wdenkf12e5682003-07-07 20:07:54 +0000116
Jon Loeliger26946902007-07-04 22:30:50 -0500117#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000119#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000121#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
123#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
124#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf12e5682003-07-07 20:07:54 +0000125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
127#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf12e5682003-07-07 20:07:54 +0000128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf12e5682003-07-07 20:07:54 +0000130
wdenkf12e5682003-07-07 20:07:54 +0000131/*
132 * Low Level Configuration Settings
133 * (address mappings, register initial values, etc.)
134 * You should know what you are doing if you make changes here.
135 */
136/*-----------------------------------------------------------------------
137 * Internal Memory Mapped Register
138 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf12e5682003-07-07 20:07:54 +0000140
141/*-----------------------------------------------------------------------
142 * Definitions for initial stack pointer and data area (in DPRAM)
143 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200145#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200146#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf12e5682003-07-07 20:07:54 +0000148
149/*-----------------------------------------------------------------------
150 * Start addresses for the final memory configuration
151 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf12e5682003-07-07 20:07:54 +0000153 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_SDRAM_BASE 0x00000000
155#define CONFIG_SYS_FLASH_BASE 0x40000000
156#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
157#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
158#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf12e5682003-07-07 20:07:54 +0000159
160/*
161 * For booting Linux, the board info and command line data
162 * have to be in the first 8 MB of memory, since this is
163 * the maximum mapped by the Linux kernel during initialization.
164 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf12e5682003-07-07 20:07:54 +0000166
167/*-----------------------------------------------------------------------
168 * FLASH organization
169 */
wdenkf12e5682003-07-07 20:07:54 +0000170
Martin Krausee318d9e2007-09-27 11:10:08 +0200171/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200173#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
175#define CONFIG_SYS_FLASH_EMPTY_INFO
176#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
177#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
178#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkf12e5682003-07-07 20:07:54 +0000179
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200180#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200181#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
182#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
183#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
wdenkf12e5682003-07-07 20:07:54 +0000184
185/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200186#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
187#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf12e5682003-07-07 20:07:54 +0000188
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200190
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200191#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
192
wdenkf12e5682003-07-07 20:07:54 +0000193/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200194 * Dynamic MTD partition support
195 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100196#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200197#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
198#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200199#define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
200
201#define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
202 "128k(dtb)," \
203 "1920k(kernel)," \
204 "5632(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200205 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200206
207/*-----------------------------------------------------------------------
wdenkf12e5682003-07-07 20:07:54 +0000208 * Hardware Information Block
209 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
211#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
212#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf12e5682003-07-07 20:07:54 +0000213
214/*-----------------------------------------------------------------------
215 * Cache Configuration
216 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500218#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf12e5682003-07-07 20:07:54 +0000220#endif
221
222/*-----------------------------------------------------------------------
223 * SYPCR - System Protection Control 11-9
224 * SYPCR can only be written once after reset!
225 *-----------------------------------------------------------------------
226 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
227 */
228#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf12e5682003-07-07 20:07:54 +0000230 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
231#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf12e5682003-07-07 20:07:54 +0000233#endif
234
235/*-----------------------------------------------------------------------
236 * SIUMCR - SIU Module Configuration 11-6
237 *-----------------------------------------------------------------------
238 * PCMCIA config., multi-function pin tri-state
239 */
240#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000242#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf12e5682003-07-07 20:07:54 +0000244#endif /* CONFIG_CAN_DRIVER */
245
246/*-----------------------------------------------------------------------
247 * TBSCR - Time Base Status and Control 11-26
248 *-----------------------------------------------------------------------
249 * Clear Reference Interrupt Status, Timebase freezing enabled
250 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf12e5682003-07-07 20:07:54 +0000252
253/*-----------------------------------------------------------------------
254 * RTCSC - Real-Time Clock Status and Control Register 11-27
255 *-----------------------------------------------------------------------
256 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf12e5682003-07-07 20:07:54 +0000258
259/*-----------------------------------------------------------------------
260 * PISCR - Periodic Interrupt Status and Control 11-31
261 *-----------------------------------------------------------------------
262 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
263 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf12e5682003-07-07 20:07:54 +0000265
266/*-----------------------------------------------------------------------
267 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
268 *-----------------------------------------------------------------------
269 * Reset PLL lock status sticky bit, timer expired status bit and timer
270 * interrupt status bit
wdenkf12e5682003-07-07 20:07:54 +0000271 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf12e5682003-07-07 20:07:54 +0000273
274/*-----------------------------------------------------------------------
275 * SCCR - System Clock and reset Control Register 15-27
276 *-----------------------------------------------------------------------
277 * Set clock output, timebase and RTC source and divider,
278 * power management and some other internal clocks
279 */
280#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf12e5682003-07-07 20:07:54 +0000282 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
283 SCCR_DFALCD00)
wdenkf12e5682003-07-07 20:07:54 +0000284
285/*-----------------------------------------------------------------------
286 * PCMCIA stuff
287 *-----------------------------------------------------------------------
288 *
289 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
291#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
292#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
293#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
294#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
295#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
296#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
297#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf12e5682003-07-07 20:07:54 +0000298
299/*-----------------------------------------------------------------------
300 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
301 *-----------------------------------------------------------------------
302 */
303
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000304#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkf12e5682003-07-07 20:07:54 +0000305#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
306
307#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
308#undef CONFIG_IDE_LED /* LED for ide not supported */
309#undef CONFIG_IDE_RESET /* reset for ide not supported */
310
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
312#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf12e5682003-07-07 20:07:54 +0000313
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf12e5682003-07-07 20:07:54 +0000315
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf12e5682003-07-07 20:07:54 +0000317
318/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000320
321/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf12e5682003-07-07 20:07:54 +0000323
324/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf12e5682003-07-07 20:07:54 +0000326
327/*-----------------------------------------------------------------------
328 *
329 *-----------------------------------------------------------------------
330 *
331 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_DER 0
wdenkf12e5682003-07-07 20:07:54 +0000333
334/*
335 * Init Memory Controller:
336 *
337 * BR0/1 and OR0/1 (FLASH)
338 */
339
340#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
341#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
342
343/* used to re-map FLASH both when starting from SRAM or FLASH:
344 * restrict access enough to keep SRAM working (if any)
345 * but not too much to meddle with FLASH accesses
346 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
348#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf12e5682003-07-07 20:07:54 +0000349
350/*
351 * FLASH timing:
352 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf12e5682003-07-07 20:07:54 +0000354 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf12e5682003-07-07 20:07:54 +0000355
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
357#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
358#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000359
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
361#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
362#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000363
364/*
365 * BR2/3 and OR2/3 (SDRAM)
366 *
367 */
368#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
369#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
370#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
371
372/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200373#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf12e5682003-07-07 20:07:54 +0000374
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
376#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000377
378#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
380#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf12e5682003-07-07 20:07:54 +0000381#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
383#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
384#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
385#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf12e5682003-07-07 20:07:54 +0000386 BR_PS_8 | BR_MS_UPMB | BR_V )
387#endif /* CONFIG_CAN_DRIVER */
388
389/*
390 * Memory Periodic Timer Prescaler
391 *
392 * The Divider for PTA (refresh timer) configuration is based on an
393 * example SDRAM configuration (64 MBit, one bank). The adjustment to
394 * the number of chip selects (NCS) and the actually needed refresh
395 * rate is done by setting MPTPR.
396 *
397 * PTA is calculated from
398 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
399 *
400 * gclk CPU clock (not bus clock!)
401 * Trefresh Refresh cycle * 4 (four word bursts used)
402 *
403 * 4096 Rows from SDRAM example configuration
404 * 1000 factor s -> ms
405 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
406 * 4 Number of refresh cycles per period
407 * 64 Refresh cycle in ms per number of rows
408 * --------------------------------------------
409 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
410 *
411 * 50 MHz => 50.000.000 / Divider = 98
412 * 66 Mhz => 66.000.000 / Divider = 129
413 * 80 Mhz => 80.000.000 / Divider = 156
414 */
wdenke9132ea2004-04-24 23:23:30 +0000415
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
417#define CONFIG_SYS_MAMR_PTA 98
wdenkf12e5682003-07-07 20:07:54 +0000418
419/*
420 * For 16 MBit, refresh rates could be 31.3 us
421 * (= 64 ms / 2K = 125 / quad bursts).
422 * For a simpler initialization, 15.6 us is used instead.
423 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
425 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf12e5682003-07-07 20:07:54 +0000426 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
428#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000429
430/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
432#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf12e5682003-07-07 20:07:54 +0000433
434/*
435 * MAMR settings for SDRAM
436 */
437
438/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000440 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
441 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
442/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf12e5682003-07-07 20:07:54 +0000444 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
445 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
446
Heiko Schocher7026ead2010-02-09 15:50:27 +0100447#define CONFIG_HWCONFIG 1
448
wdenkf12e5682003-07-07 20:07:54 +0000449#endif /* __CONFIG_H */