blob: bb865b7f4c30eb71f9dfda6b5e4c277e8b7717b7 [file] [log] [blame]
Marek Vasutec33de32011-11-08 23:18:14 +00001/*
2 * Freescale i.MX28 SPI driver
3 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 * NOTE: This driver only supports the SPI-controller chipselects,
23 * GPIO driven chipselects are not supported.
24 */
25
26#include <common.h>
27#include <malloc.h>
28#include <spi.h>
29#include <asm/errno.h>
30#include <asm/io.h>
31#include <asm/arch/clock.h>
32#include <asm/arch/imx-regs.h>
33#include <asm/arch/sys_proto.h>
Marek Vasut7c5e6f72012-07-09 00:48:33 +000034#include <asm/arch/dma.h>
Marek Vasutec33de32011-11-08 23:18:14 +000035
36#define MXS_SPI_MAX_TIMEOUT 1000000
37#define MXS_SPI_PORT_OFFSET 0x2000
Fabio Estevam148ca642012-04-23 08:30:50 +000038#define MXS_SSP_CHIPSELECT_MASK 0x00300000
39#define MXS_SSP_CHIPSELECT_SHIFT 20
Marek Vasutec33de32011-11-08 23:18:14 +000040
Marek Vasut7c5e6f72012-07-09 00:48:33 +000041#define MXSSSP_SMALL_TRANSFER 512
42
43/*
44 * CONFIG_MXS_SPI_DMA_ENABLE: Experimental mixed PIO/DMA support for MXS SPI
45 * host. Use with utmost caution!
46 *
47 * Enabling this is not yet recommended since this
48 * still doesn't support transfers to/from unaligned
49 * addresses. Therefore this driver will not work
50 * for example with saving environment. This is
51 * caused by DMA alignment constraints on MXS.
52 */
53
Marek Vasutec33de32011-11-08 23:18:14 +000054struct mxs_spi_slave {
55 struct spi_slave slave;
56 uint32_t max_khz;
57 uint32_t mode;
Otavio Salvador9c471142012-08-05 09:05:31 +000058 struct mxs_ssp_regs *regs;
Marek Vasutec33de32011-11-08 23:18:14 +000059};
60
61static inline struct mxs_spi_slave *to_mxs_slave(struct spi_slave *slave)
62{
63 return container_of(slave, struct mxs_spi_slave, slave);
64}
65
66void spi_init(void)
67{
68}
69
Fabio Estevam79cb14a2012-04-23 08:30:49 +000070int spi_cs_is_valid(unsigned int bus, unsigned int cs)
71{
72 /* MXS SPI: 4 ports and 3 chip selects maximum */
73 if (bus > 3 || cs > 2)
74 return 0;
75 else
76 return 1;
77}
78
Marek Vasutec33de32011-11-08 23:18:14 +000079struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
80 unsigned int max_hz, unsigned int mode)
81{
82 struct mxs_spi_slave *mxs_slave;
Otavio Salvador9c471142012-08-05 09:05:31 +000083 struct mxs_ssp_regs *ssp_regs;
Fabio Estevam148ca642012-04-23 08:30:50 +000084 int reg;
Marek Vasutec33de32011-11-08 23:18:14 +000085
Fabio Estevam79cb14a2012-04-23 08:30:49 +000086 if (!spi_cs_is_valid(bus, cs)) {
87 printf("mxs_spi: invalid bus %d / chip select %d\n", bus, cs);
Marek Vasutec33de32011-11-08 23:18:14 +000088 return NULL;
89 }
90
Matt Sealeyc6b52c42012-08-17 08:15:11 +000091 mxs_slave = calloc(sizeof(struct mxs_spi_slave), 1);
Marek Vasutec33de32011-11-08 23:18:14 +000092 if (!mxs_slave)
93 return NULL;
94
Marek Vasut7c5e6f72012-07-09 00:48:33 +000095 if (mxs_dma_init_channel(bus))
96 goto err_init;
97
Marek Vasutec33de32011-11-08 23:18:14 +000098 mxs_slave->slave.bus = bus;
99 mxs_slave->slave.cs = cs;
100 mxs_slave->max_khz = max_hz / 1000;
101 mxs_slave->mode = mode;
Marek Vasut14e26bc2013-01-11 03:19:02 +0000102 mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
Fabio Estevam148ca642012-04-23 08:30:50 +0000103 ssp_regs = mxs_slave->regs;
Marek Vasutec33de32011-11-08 23:18:14 +0000104
Fabio Estevam148ca642012-04-23 08:30:50 +0000105 reg = readl(&ssp_regs->hw_ssp_ctrl0);
106 reg &= ~(MXS_SSP_CHIPSELECT_MASK);
107 reg |= cs << MXS_SSP_CHIPSELECT_SHIFT;
108
109 writel(reg, &ssp_regs->hw_ssp_ctrl0);
Marek Vasutec33de32011-11-08 23:18:14 +0000110 return &mxs_slave->slave;
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000111
112err_init:
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000113 free(mxs_slave);
114 return NULL;
Marek Vasutec33de32011-11-08 23:18:14 +0000115}
116
117void spi_free_slave(struct spi_slave *slave)
118{
119 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
120 free(mxs_slave);
121}
122
123int spi_claim_bus(struct spi_slave *slave)
124{
125 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
Otavio Salvador9c471142012-08-05 09:05:31 +0000126 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
Marek Vasutec33de32011-11-08 23:18:14 +0000127 uint32_t reg = 0;
128
Otavio Salvadorfa7a51c2012-08-13 09:53:12 +0000129 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
Marek Vasutec33de32011-11-08 23:18:14 +0000130
131 writel(SSP_CTRL0_BUS_WIDTH_ONE_BIT, &ssp_regs->hw_ssp_ctrl0);
132
133 reg = SSP_CTRL1_SSP_MODE_SPI | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS;
134 reg |= (mxs_slave->mode & SPI_CPOL) ? SSP_CTRL1_POLARITY : 0;
135 reg |= (mxs_slave->mode & SPI_CPHA) ? SSP_CTRL1_PHASE : 0;
136 writel(reg, &ssp_regs->hw_ssp_ctrl1);
137
138 writel(0, &ssp_regs->hw_ssp_cmd0);
139
Otavio Salvadorbf48fcb2013-01-11 03:19:03 +0000140 mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
Marek Vasutec33de32011-11-08 23:18:14 +0000141
142 return 0;
143}
144
145void spi_release_bus(struct spi_slave *slave)
146{
147}
148
Otavio Salvador9c471142012-08-05 09:05:31 +0000149static void mxs_spi_start_xfer(struct mxs_ssp_regs *ssp_regs)
Marek Vasutec33de32011-11-08 23:18:14 +0000150{
151 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_set);
152 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_clr);
153}
154
Otavio Salvador9c471142012-08-05 09:05:31 +0000155static void mxs_spi_end_xfer(struct mxs_ssp_regs *ssp_regs)
Marek Vasutec33de32011-11-08 23:18:14 +0000156{
157 writel(SSP_CTRL0_LOCK_CS, &ssp_regs->hw_ssp_ctrl0_clr);
158 writel(SSP_CTRL0_IGNORE_CRC, &ssp_regs->hw_ssp_ctrl0_set);
159}
160
Marek Vasutccd4d5a2012-07-09 00:48:32 +0000161static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
162 char *data, int length, int write, unsigned long flags)
Marek Vasutec33de32011-11-08 23:18:14 +0000163{
Otavio Salvador9c471142012-08-05 09:05:31 +0000164 struct mxs_ssp_regs *ssp_regs = slave->regs;
Marek Vasutc7065fa2012-07-09 00:48:31 +0000165
Marek Vasutec33de32011-11-08 23:18:14 +0000166 if (flags & SPI_XFER_BEGIN)
167 mxs_spi_start_xfer(ssp_regs);
168
Marek Vasutccd4d5a2012-07-09 00:48:32 +0000169 while (length--) {
Marek Vasutec33de32011-11-08 23:18:14 +0000170 /* We transfer 1 byte */
171 writel(1, &ssp_regs->hw_ssp_xfer_size);
172
Marek Vasutccd4d5a2012-07-09 00:48:32 +0000173 if ((flags & SPI_XFER_END) && !length)
Marek Vasutec33de32011-11-08 23:18:14 +0000174 mxs_spi_end_xfer(ssp_regs);
175
Marek Vasutc7065fa2012-07-09 00:48:31 +0000176 if (write)
Marek Vasutec33de32011-11-08 23:18:14 +0000177 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_clr);
178 else
179 writel(SSP_CTRL0_READ, &ssp_regs->hw_ssp_ctrl0_set);
180
181 writel(SSP_CTRL0_RUN, &ssp_regs->hw_ssp_ctrl0_set);
182
Otavio Salvadorfa7a51c2012-08-13 09:53:12 +0000183 if (mxs_wait_mask_set(&ssp_regs->hw_ssp_ctrl0_reg,
Marek Vasutec33de32011-11-08 23:18:14 +0000184 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
185 printf("MXS SPI: Timeout waiting for start\n");
Fabio Estevamd9fb6a42012-03-18 17:23:35 +0000186 return -ETIMEDOUT;
Marek Vasutec33de32011-11-08 23:18:14 +0000187 }
188
Marek Vasutc7065fa2012-07-09 00:48:31 +0000189 if (write)
190 writel(*data++, &ssp_regs->hw_ssp_data);
Marek Vasutec33de32011-11-08 23:18:14 +0000191
192 writel(SSP_CTRL0_DATA_XFER, &ssp_regs->hw_ssp_ctrl0_set);
193
Marek Vasutc7065fa2012-07-09 00:48:31 +0000194 if (!write) {
Otavio Salvadorfa7a51c2012-08-13 09:53:12 +0000195 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_status_reg,
Marek Vasutec33de32011-11-08 23:18:14 +0000196 SSP_STATUS_FIFO_EMPTY, MXS_SPI_MAX_TIMEOUT)) {
197 printf("MXS SPI: Timeout waiting for data\n");
Fabio Estevamd9fb6a42012-03-18 17:23:35 +0000198 return -ETIMEDOUT;
Marek Vasutec33de32011-11-08 23:18:14 +0000199 }
200
Marek Vasutc7065fa2012-07-09 00:48:31 +0000201 *data = readl(&ssp_regs->hw_ssp_data);
202 data++;
Marek Vasutec33de32011-11-08 23:18:14 +0000203 }
204
Otavio Salvadorfa7a51c2012-08-13 09:53:12 +0000205 if (mxs_wait_mask_clr(&ssp_regs->hw_ssp_ctrl0_reg,
Marek Vasutec33de32011-11-08 23:18:14 +0000206 SSP_CTRL0_RUN, MXS_SPI_MAX_TIMEOUT)) {
207 printf("MXS SPI: Timeout waiting for finish\n");
Fabio Estevamd9fb6a42012-03-18 17:23:35 +0000208 return -ETIMEDOUT;
Marek Vasutec33de32011-11-08 23:18:14 +0000209 }
210 }
211
212 return 0;
Marek Vasutccd4d5a2012-07-09 00:48:32 +0000213}
214
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000215static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
216 char *data, int length, int write, unsigned long flags)
217{
Marek Vasut2c432142012-08-21 16:17:27 +0000218 const int xfer_max_sz = 0xff00;
219 const int desc_count = DIV_ROUND_UP(length, xfer_max_sz) + 1;
Otavio Salvador9c471142012-08-05 09:05:31 +0000220 struct mxs_ssp_regs *ssp_regs = slave->regs;
Marek Vasut2c432142012-08-21 16:17:27 +0000221 struct mxs_dma_desc *dp;
222 uint32_t ctrl0;
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000223 uint32_t cache_data_count;
Marek Vasut88d15552012-08-31 16:07:59 +0000224 const uint32_t dstart = (uint32_t)data;
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000225 int dmach;
Marek Vasut2c432142012-08-21 16:17:27 +0000226 int tl;
Marek Vasute9f7eaf2012-08-31 16:08:00 +0000227 int ret = 0;
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000228
Marek Vasut2c432142012-08-21 16:17:27 +0000229 ALLOC_CACHE_ALIGN_BUFFER(struct mxs_dma_desc, desc, desc_count);
230
231 memset(desc, 0, sizeof(struct mxs_dma_desc) * desc_count);
232
233 ctrl0 = readl(&ssp_regs->hw_ssp_ctrl0);
234 ctrl0 |= SSP_CTRL0_DATA_XFER;
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000235
236 if (flags & SPI_XFER_BEGIN)
237 ctrl0 |= SSP_CTRL0_LOCK_CS;
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000238 if (!write)
239 ctrl0 |= SSP_CTRL0_READ;
240
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000241 if (length % ARCH_DMA_MINALIGN)
242 cache_data_count = roundup(length, ARCH_DMA_MINALIGN);
243 else
244 cache_data_count = length;
245
Marek Vasut88d15552012-08-31 16:07:59 +0000246 /* Flush data to DRAM so DMA can pick them up */
Marek Vasut2c432142012-08-21 16:17:27 +0000247 if (write)
Marek Vasut88d15552012-08-31 16:07:59 +0000248 flush_dcache_range(dstart, dstart + cache_data_count);
249
250 /* Invalidate the area, so no writeback into the RAM races with DMA */
251 invalidate_dcache_range(dstart, dstart + cache_data_count);
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000252
253 dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + slave->slave.bus;
Marek Vasut2c432142012-08-21 16:17:27 +0000254
255 dp = desc;
256 while (length) {
257 dp->address = (dma_addr_t)dp;
258 dp->cmd.address = (dma_addr_t)data;
259
260 /*
261 * This is correct, even though it does indeed look insane.
262 * I hereby have to, wholeheartedly, thank Freescale Inc.,
263 * for always inventing insane hardware and keeping me busy
264 * and employed ;-)
265 */
266 if (write)
267 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_READ;
268 else
269 dp->cmd.data = MXS_DMA_DESC_COMMAND_DMA_WRITE;
270
271 /*
272 * The DMA controller can transfer large chunks (64kB) at
273 * time by setting the transfer length to 0. Setting tl to
274 * 0x10000 will overflow below and make .data contain 0.
275 * Otherwise, 0xff00 is the transfer maximum.
276 */
277 if (length >= 0x10000)
278 tl = 0x10000;
279 else
280 tl = min(length, xfer_max_sz);
281
282 dp->cmd.data |=
Marek Vasute9f7eaf2012-08-31 16:08:00 +0000283 ((tl & 0xffff) << MXS_DMA_DESC_BYTES_OFFSET) |
284 (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
Marek Vasut2c432142012-08-21 16:17:27 +0000285 MXS_DMA_DESC_HALT_ON_TERMINATE |
286 MXS_DMA_DESC_TERMINATE_FLUSH;
Marek Vasut2c432142012-08-21 16:17:27 +0000287
288 data += tl;
289 length -= tl;
290
Marek Vasute9f7eaf2012-08-31 16:08:00 +0000291 if (!length) {
292 dp->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM;
293
294 if (flags & SPI_XFER_END) {
295 ctrl0 &= ~SSP_CTRL0_LOCK_CS;
296 ctrl0 |= SSP_CTRL0_IGNORE_CRC;
297 }
298 }
299
300 /*
301 * Write CTRL0, CMD0, CMD1, XFER_SIZE registers. It is
302 * essential that the XFER_SIZE register is written on
303 * a per-descriptor basis with the same size as is the
304 * descriptor!
305 */
306 dp->cmd.pio_words[0] = ctrl0;
307 dp->cmd.pio_words[1] = 0;
308 dp->cmd.pio_words[2] = 0;
309 dp->cmd.pio_words[3] = tl;
310
Marek Vasut2c432142012-08-21 16:17:27 +0000311 mxs_dma_desc_append(dmach, dp);
312
313 dp++;
314 }
315
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000316 if (mxs_dma_go(dmach))
Marek Vasute9f7eaf2012-08-31 16:08:00 +0000317 ret = -EINVAL;
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000318
319 /* The data arrived into DRAM, invalidate cache over them */
Marek Vasut88d15552012-08-31 16:07:59 +0000320 if (!write)
321 invalidate_dcache_range(dstart, dstart + cache_data_count);
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000322
Marek Vasute9f7eaf2012-08-31 16:08:00 +0000323 return ret;
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000324}
325
Marek Vasutccd4d5a2012-07-09 00:48:32 +0000326int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
327 const void *dout, void *din, unsigned long flags)
328{
329 struct mxs_spi_slave *mxs_slave = to_mxs_slave(slave);
Otavio Salvador9c471142012-08-05 09:05:31 +0000330 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs;
Marek Vasutccd4d5a2012-07-09 00:48:32 +0000331 int len = bitlen / 8;
332 char dummy;
333 int write = 0;
334 char *data = NULL;
335
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000336#ifdef CONFIG_MXS_SPI_DMA_ENABLE
337 int dma = 1;
338#else
339 int dma = 0;
340#endif
341
Marek Vasutccd4d5a2012-07-09 00:48:32 +0000342 if (bitlen == 0) {
343 if (flags & SPI_XFER_END) {
344 din = (void *)&dummy;
345 len = 1;
346 } else
347 return 0;
348 }
349
350 /* Half-duplex only */
351 if (din && dout)
352 return -EINVAL;
353 /* No data */
354 if (!din && !dout)
355 return 0;
356
357 if (dout) {
358 data = (char *)dout;
359 write = 1;
360 } else if (din) {
361 data = (char *)din;
362 write = 0;
363 }
364
Marek Vasut7c5e6f72012-07-09 00:48:33 +0000365 /*
366 * Check for alignment, if the buffer is aligned, do DMA transfer,
367 * PIO otherwise. This is a temporary workaround until proper bounce
368 * buffer is in place.
369 */
370 if (dma) {
371 if (((uint32_t)data) & (ARCH_DMA_MINALIGN - 1))
372 dma = 0;
373 if (((uint32_t)len) & (ARCH_DMA_MINALIGN - 1))
374 dma = 0;
375 }
376
377 if (!dma || (len < MXSSSP_SMALL_TRANSFER)) {
378 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr);
379 return mxs_spi_xfer_pio(mxs_slave, data, len, write, flags);
380 } else {
381 writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set);
382 return mxs_spi_xfer_dma(mxs_slave, data, len, write, flags);
383 }
Marek Vasutec33de32011-11-08 23:18:14 +0000384}