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Chin Liang See68e17472013-08-07 10:08:03 -05001/*
2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7
8#include <common.h>
9#include <asm/io.h>
10#include <asm/arch/reset_manager.h>
Marek Vasutabb25f42014-09-08 14:08:45 +020011#include <asm/arch/fpga_manager.h>
Chin Liang See68e17472013-08-07 10:08:03 -050012
13DECLARE_GLOBAL_DATA_PTR;
14
15static const struct socfpga_reset_manager *reset_manager_base =
16 (void *)SOCFPGA_RSTMGR_ADDRESS;
17
Marek Vasutbdfc2ef2015-07-09 02:45:15 +020018/* Assert or de-assert SoCFPGA reset manager reset. */
19void socfpga_per_reset(u32 reset, int set)
20{
21 const void *reg;
22
23 if (RSTMGR_BANK(reset) == 0)
24 reg = &reset_manager_base->mpu_mod_reset;
25 else if (RSTMGR_BANK(reset) == 1)
26 reg = &reset_manager_base->per_mod_reset;
27 else if (RSTMGR_BANK(reset) == 2)
28 reg = &reset_manager_base->per2_mod_reset;
29 else if (RSTMGR_BANK(reset) == 3)
30 reg = &reset_manager_base->brg_mod_reset;
31 else if (RSTMGR_BANK(reset) == 4)
32 reg = &reset_manager_base->misc_mod_reset;
33 else /* Invalid reset register, do nothing */
34 return;
35
36 if (set)
37 setbits_le32(reg, 1 << RSTMGR_RESET(reset));
38 else
39 clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
40}
41
Pavel Machekde6da922014-09-09 14:03:28 +020042/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
43void socfpga_watchdog_reset(void)
44{
45 /* assert reset for watchdog */
Marek Vasutbdfc2ef2015-07-09 02:45:15 +020046 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
Pavel Machekde6da922014-09-09 14:03:28 +020047
48 /* deassert watchdog from reset (watchdog in not running state) */
Marek Vasutbdfc2ef2015-07-09 02:45:15 +020049 socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
Pavel Machekde6da922014-09-09 14:03:28 +020050}
51
Chin Liang See68e17472013-08-07 10:08:03 -050052/*
53 * Write the reset manager register to cause reset
54 */
55void reset_cpu(ulong addr)
56{
57 /* request a warm reset */
58 writel((1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB),
59 &reset_manager_base->ctrl);
60 /*
61 * infinite loop here as watchdog will trigger and reset
62 * the processor
63 */
64 while (1)
65 ;
66}
67
68/*
69 * Release peripherals from reset based on handoff
70 */
71void reset_deassert_peripherals_handoff(void)
72{
73 writel(0, &reset_manager_base->per_mod_reset);
74}
Marek Vasute9d6a202014-09-08 14:08:45 +020075
Marek Vasutabb25f42014-09-08 14:08:45 +020076#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
77void socfpga_bridges_reset(int enable)
78{
79 /* For SoCFPGA-VT, this is NOP. */
80}
81#else
82
83#define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
84#define L3REGS_REMAP_HPS2FPGA_MASK 0x08
85#define L3REGS_REMAP_OCRAM_MASK 0x01
86
87void socfpga_bridges_reset(int enable)
88{
89 const uint32_t l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
90 L3REGS_REMAP_HPS2FPGA_MASK |
91 L3REGS_REMAP_OCRAM_MASK;
92
93 if (enable) {
94 /* brdmodrst */
95 writel(0xffffffff, &reset_manager_base->brg_mod_reset);
96 } else {
97 /* Check signal from FPGA. */
98 if (fpgamgr_poll_fpga_ready()) {
99 /* FPGA not ready. Wait for watchdog timeout. */
100 printf("%s: fpga not ready, hanging.\n", __func__);
101 hang();
102 }
103
104 /* brdmodrst */
105 writel(0, &reset_manager_base->brg_mod_reset);
106
107 /* Remap the bridges into memory map */
108 writel(l3mask, SOCFPGA_L3REGS_ADDRESS);
109 }
110}
111#endif
112
Marek Vasute9d6a202014-09-08 14:08:45 +0200113/* Change the reset state for EMAC 0 and EMAC 1 */
114void socfpga_emac_reset(int enable)
115{
Marek Vasute9d6a202014-09-08 14:08:45 +0200116 if (enable) {
Marek Vasutbdfc2ef2015-07-09 02:45:15 +0200117 socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
118 socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
Marek Vasute9d6a202014-09-08 14:08:45 +0200119 } else {
120#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
Marek Vasutbdfc2ef2015-07-09 02:45:15 +0200121 socfpga_per_reset(SOCFPGA_RESET(EMAC0), 0);
Marek Vasute9d6a202014-09-08 14:08:45 +0200122#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
Marek Vasutbdfc2ef2015-07-09 02:45:15 +0200123 socfpga_per_reset(SOCFPGA_RESET(EMAC1), 0);
Marek Vasute9d6a202014-09-08 14:08:45 +0200124#endif
125 }
126}
Stefan Roesea877bec2014-11-07 13:50:30 +0100127
128/* SPI Master enable (its held in reset by the preloader) */
129void socfpga_spim_enable(void)
130{
Marek Vasutbdfc2ef2015-07-09 02:45:15 +0200131 socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
132 socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
Stefan Roesea877bec2014-11-07 13:50:30 +0100133}
Dinh Nguyenc218f852015-03-30 17:01:04 -0500134
135/* Bring UART0 out of reset. */
136void socfpga_uart0_enable(void)
137{
Marek Vasutbdfc2ef2015-07-09 02:45:15 +0200138 socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
Dinh Nguyenc218f852015-03-30 17:01:04 -0500139}
140
141/* Bring SDRAM controller out of reset. */
142void socfpga_sdram_enable(void)
143{
Marek Vasutbdfc2ef2015-07-09 02:45:15 +0200144 socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
Dinh Nguyenc218f852015-03-30 17:01:04 -0500145}
146
147/* Bring OSC1 timer out of reset. */
148void socfpga_osc1timer_enable(void)
149{
Marek Vasutbdfc2ef2015-07-09 02:45:15 +0200150 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
Dinh Nguyenc218f852015-03-30 17:01:04 -0500151}