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Manivannan Sadhasivam93ffa2b2019-05-02 13:26:44 +05301// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2/*
3 * Copyright : STMicroelectronics 2018
4 *
5 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
7 */
8
9#include <dt-bindings/clock/stm32mp1-clksrc.h>
10#include "stm32mp157-u-boot.dtsi"
11#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
12
13/ {
14 aliases {
15 mmc0 = &sdmmc1;
16 mmc1 = &sdmmc2;
17 usb0 = &usbotg_hs;
18 };
19
20 config {
21 u-boot,boot-led = "led1";
22 u-boot,error-led = "led4";
23 };
24};
25
26&i2c4 {
27 u-boot,dm-pre-reloc;
28};
29
30&i2c4_pins_a {
31 u-boot,dm-pre-reloc;
32 pins {
33 u-boot,dm-pre-reloc;
34 };
35};
36
37&pmic {
38 u-boot,dm-pre-reloc;
39};
40
41&rcc {
42 st,clksrc = <
43 CLK_MPU_PLL1P
44 CLK_AXI_PLL2P
45 CLK_MCU_PLL3P
46 CLK_PLL12_HSE
47 CLK_PLL3_HSE
48 CLK_PLL4_HSE
49 CLK_RTC_LSE
50 CLK_MCO1_DISABLED
51 CLK_MCO2_DISABLED
52 >;
53
54 st,clkdiv = <
55 1 /*MPU*/
56 0 /*AXI*/
57 0 /*MCU*/
58 1 /*APB1*/
59 1 /*APB2*/
60 1 /*APB3*/
61 1 /*APB4*/
62 2 /*APB5*/
63 23 /*RTC*/
64 0 /*MCO1*/
65 0 /*MCO2*/
66 >;
67
68 st,pkcs = <
69 CLK_CKPER_HSE
70 CLK_FMC_ACLK
71 CLK_QSPI_ACLK
72 CLK_ETH_DISABLED
73 CLK_SDMMC12_PLL4P
74 CLK_DSI_DSIPLL
75 CLK_STGEN_HSE
76 CLK_USBPHY_HSE
77 CLK_SPI2S1_PLL3Q
78 CLK_SPI2S23_PLL3Q
79 CLK_SPI45_HSI
80 CLK_SPI6_HSI
81 CLK_I2C46_HSI
82 CLK_SDMMC3_PLL4P
83 CLK_USBO_USBPHY
84 CLK_ADC_CKPER
85 CLK_CEC_LSE
86 CLK_I2C12_HSI
87 CLK_I2C35_HSI
88 CLK_UART1_HSI
89 CLK_UART24_HSI
90 CLK_UART35_HSI
91 CLK_UART6_HSI
92 CLK_UART78_HSI
93 CLK_SPDIF_PLL4P
94 CLK_FDCAN_PLL4Q
95 CLK_SAI1_PLL3Q
96 CLK_SAI2_PLL3Q
97 CLK_SAI3_PLL3Q
98 CLK_SAI4_PLL3Q
99 CLK_RNG1_LSI
100 CLK_RNG2_LSI
101 CLK_LPTIM1_PCLK1
102 CLK_LPTIM23_PCLK3
103 CLK_LPTIM45_LSE
104 >;
105
106 /* VCO = 1300.0 MHz => P = 650 (CPU) */
107 pll1: st,pll@0 {
108 cfg = < 2 80 0 0 0 PQR(1,0,0) >;
109 frac = < 0x800 >;
110 u-boot,dm-pre-reloc;
111 };
112
113 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
114 pll2: st,pll@1 {
115 cfg = < 2 65 1 0 0 PQR(1,1,1) >;
116 frac = < 0x1400 >;
117 u-boot,dm-pre-reloc;
118 };
119
120 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
121 pll3: st,pll@2 {
122 cfg = < 1 33 1 16 36 PQR(1,1,1) >;
123 frac = < 0x1a04 >;
124 u-boot,dm-pre-reloc;
125 };
126
127 /* VCO = 480.0 MHz => P = 120, Q = 40, R = 96 */
128 pll4: st,pll@3 {
129 cfg = < 1 39 3 11 4 PQR(1,1,1) >;
130 u-boot,dm-pre-reloc;
131 };
132};
133
134&sdmmc1 {
135 u-boot,dm-spl;
136};
137
138&sdmmc1_b4_pins_a {
139 u-boot,dm-spl;
140 pins {
141 u-boot,dm-spl;
142 };
143};
144
145&sdmmc1_dir_pins_a {
146 u-boot,dm-spl;
147 pins {
148 u-boot,dm-spl;
149 };
150};
151
152&sdmmc2 {
153 u-boot,dm-spl;
154};
155
156&sdmmc2_b4_pins_a {
157 u-boot,dm-spl;
158 pins {
159 u-boot,dm-spl;
160 };
161};
162
163&sdmmc2_d47_pins_a {
164 u-boot,dm-spl;
165 pins {
166 u-boot,dm-spl;
167 };
168};
169
170&uart4 {
171 u-boot,dm-pre-reloc;
172};
173
174&uart4_pins_b {
175 u-boot,dm-pre-reloc;
176 pins1 {
177 u-boot,dm-pre-reloc;
178 };
179 pins2 {
180 u-boot,dm-pre-reloc;
181 };
182};
183
184&usbotg_hs {
185 u-boot,force-b-session-valid;
186 hnp-srp-disable;
187};
188
189&v3v3 {
190 regulator-always-on;
191};