blob: 920246d577edb0f242a1411c2556cb693910b3c2 [file] [log] [blame]
Tim Harvey23956252022-04-13 11:31:09 -07001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Gateworks Corporation
4 */
5
6#include "imx8mp-u-boot.dtsi"
7
8/ {
9 firmware {
10 optee {
11 compatible = "linaro,optee-tz";
12 method = "smc";
13 };
14 };
15
16 wdt-reboot {
17 compatible = "wdt-reboot";
18 u-boot,dm-spl;
19 wdt = <&wdog1>;
20 };
21};
22
23&eqos {
24 /delete-property/ assigned-clocks;
25 /delete-property/ assigned-clock-parents;
26 /delete-property/ assigned-clock-rates;
27};
28
29&ethphy0 {
30 reset-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>;
31 reset-delay-us = <1000>;
32 reset-post-delay-us = <300000>;
33};
34
35&fec {
36 phy-reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>;
37 phy-reset-duration = <15>;
38 phy-reset-post-delay = <100>;
39};
40
41&gpio1 {
42 u-boot,dm-spl;
43
44 dio0_hog {
45 gpio-hog;
46 input;
47 gpios = <9 GPIO_ACTIVE_LOW>;
48 line-name = "dio0";
49 };
50
51 dio1_hog {
52 gpio-hog;
53 input;
54 gpios = <11 GPIO_ACTIVE_LOW>;
55 line-name = "dio1";
56 };
57};
58
59&gpio2 {
60 u-boot,dm-spl;
61
62 pcie1_wdis_hog {
63 gpio-hog;
64 gpios = <17 GPIO_ACTIVE_HIGH>;
65 output-high;
66 line-name = "pcie1_wdis#";
67 };
68
69 pcie2_wdis_hog {
70 gpio-hog;
71 gpios = <18 GPIO_ACTIVE_HIGH>;
72 output-high;
73 line-name = "pcie2_wdis#";
74 };
75
76 pcie3_wdis_hog {
77 gpio-hog;
78 gpios = <14 GPIO_ACTIVE_HIGH>;
79 output-high;
80 line-name = "pcie3_wdis#";
81 };
82};
83
84&gpio3 {
85 u-boot,dm-spl;
86
87 m2_dis2_hog {
88 gpio-hog;
89 gpios = <0 GPIO_ACTIVE_LOW>;
90 output-high;
91 line-name = "m2_gdis#";
92 };
93
94 m2rst_hog {
95 gpio-hog;
96 gpios = <6 GPIO_ACTIVE_LOW>;
97 output-high;
98 line-name = "m2_rst#";
99 };
100
101 m2_off_hog {
102 gpio-hog;
103 gpios = <14 GPIO_ACTIVE_LOW>;
104 output-high;
105 line-name = "m2_off#";
106 };
107};
108
109&gpio4 {
110 u-boot,dm-spl;
111
112 m2_dis1_hog {
113 gpio-hog;
114 gpios = <18 GPIO_ACTIVE_LOW>;
115 output-high;
116 line-name = "m2_wdis#";
117 };
118
119 uart_rs485_hog {
120 gpio-hog;
121 gpios = <31 GPIO_ACTIVE_LOW>;
122 output-low;
123 line-name = "uart_rs485";
124 };
125};
126
127&gpio5 {
128 u-boot,dm-spl;
129
130 uart_half_hog {
131 gpio-hog;
132 gpios = <0 GPIO_ACTIVE_LOW>;
133 output-high;
134 line-name = "uart_half";
135 };
136
137 uart_term_hog {
138 gpio-hog;
139 gpios = <1 GPIO_ACTIVE_LOW>;
140 output-low;
141 line-name = "uart_term";
142 };
143};
144
145&i2c1 {
146 u-boot,dm-spl;
147};
148
149&i2c2 {
150 u-boot,dm-spl;
151};
152
153&i2c3 {
154 u-boot,dm-spl;
155};
156
157&pinctrl_i2c1 {
158 u-boot,dm-spl;
159};
160
161&pinctrl_wdog {
162 u-boot,dm-spl;
163};
164
165&usdhc2 {
166 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
167 assigned-clock-rates = <400000000>;
168 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
169 sd-uhs-ddr50;
170 sd-uhs-sdr104;
171 u-boot,dm-spl;
172};
173
174&usdhc3 {
175 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
176 assigned-clock-rates = <400000000>;
177 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
178 mmc-hs400-1_8v;
179 mmc-hs400-enhanced-strobe;
180 u-boot,dm-spl;
181};
182
183&wdog1 {
184 u-boot,dm-spl;
185};