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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass1b2fd5b2015-09-01 19:19:37 -06002/*
3 * spi driver for rockchip
4 *
Philipp Tomsich8aa6c922019-02-03 16:17:31 +01005 * (C) 2019 Theobroma Systems Design und Consulting GmbH
6 *
Simon Glass1b2fd5b2015-09-01 19:19:37 -06007 * (C) Copyright 2015 Google, Inc
8 *
9 * (C) Copyright 2008-2013 Rockchip Electronics
10 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
Simon Glass1b2fd5b2015-09-01 19:19:37 -060011 */
12
13#include <common.h>
14#include <clk.h>
15#include <dm.h>
Simon Glass6e019c42016-11-13 14:22:02 -070016#include <dt-structs.h>
Simon Glass1b2fd5b2015-09-01 19:19:37 -060017#include <errno.h>
18#include <spi.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090019#include <linux/errno.h>
Simon Glass1b2fd5b2015-09-01 19:19:37 -060020#include <asm/io.h>
Kever Yang15f09a12019-03-28 11:01:23 +080021#include <asm/arch-rockchip/clock.h>
22#include <asm/arch-rockchip/periph.h>
Simon Glass1b2fd5b2015-09-01 19:19:37 -060023#include <dm/pinctrl.h>
24#include "rk_spi.h"
25
Simon Glass1b2fd5b2015-09-01 19:19:37 -060026/* Change to 1 to output registers at the start of each transaction */
27#define DEBUG_RK_SPI 0
28
Philipp Tomsich51a644a2019-02-03 16:17:32 +010029struct rockchip_spi_params {
30 /* RXFIFO overruns and TXFIFO underruns stop the master clock */
31 bool master_manages_fifo;
32};
33
Simon Glass1b2fd5b2015-09-01 19:19:37 -060034struct rockchip_spi_platdata {
Simon Glass6e019c42016-11-13 14:22:02 -070035#if CONFIG_IS_ENABLED(OF_PLATDATA)
36 struct dtd_rockchip_rk3288_spi of_plat;
37#endif
Simon Glass1b2fd5b2015-09-01 19:19:37 -060038 s32 frequency; /* Default clock frequency, -1 for none */
39 fdt_addr_t base;
40 uint deactivate_delay_us; /* Delay to wait after deactivate */
Simon Glass183a3a02016-01-21 19:44:10 -070041 uint activate_delay_us; /* Delay to wait after activate */
Simon Glass1b2fd5b2015-09-01 19:19:37 -060042};
43
44struct rockchip_spi_priv {
45 struct rockchip_spi *regs;
Stephen Warren135aa952016-06-17 09:44:00 -060046 struct clk clk;
Simon Glass1b2fd5b2015-09-01 19:19:37 -060047 unsigned int max_freq;
48 unsigned int mode;
Simon Glass1b2fd5b2015-09-01 19:19:37 -060049 ulong last_transaction_us; /* Time of last transaction end */
Simon Glass1b2fd5b2015-09-01 19:19:37 -060050 unsigned int speed_hz;
Simon Glass28a943c2016-01-21 19:44:03 -070051 unsigned int last_speed_hz;
Simon Glass1b2fd5b2015-09-01 19:19:37 -060052 uint input_rate;
53};
54
55#define SPI_FIFO_DEPTH 32
56
57static void rkspi_dump_regs(struct rockchip_spi *regs)
58{
59 debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0));
60 debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1));
61 debug("ssienr: \t\t0x%08x\n", readl(&regs->enr));
62 debug("ser: \t\t0x%08x\n", readl(&regs->ser));
63 debug("baudr: \t\t0x%08x\n", readl(&regs->baudr));
64 debug("txftlr: \t\t0x%08x\n", readl(&regs->txftlr));
65 debug("rxftlr: \t\t0x%08x\n", readl(&regs->rxftlr));
66 debug("txflr: \t\t0x%08x\n", readl(&regs->txflr));
67 debug("rxflr: \t\t0x%08x\n", readl(&regs->rxflr));
68 debug("sr: \t\t0x%08x\n", readl(&regs->sr));
69 debug("imr: \t\t0x%08x\n", readl(&regs->imr));
70 debug("isr: \t\t0x%08x\n", readl(&regs->isr));
71 debug("dmacr: \t\t0x%08x\n", readl(&regs->dmacr));
72 debug("dmatdlr: \t0x%08x\n", readl(&regs->dmatdlr));
73 debug("dmardlr: \t0x%08x\n", readl(&regs->dmardlr));
74}
75
76static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
77{
78 writel(enable ? 1 : 0, &regs->enr);
79}
80
81static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
82{
Philipp Tomsich9fc354e2017-04-20 22:05:52 +020083 /*
84 * We should try not to exceed the speed requested by the caller:
85 * when selecting a divider, we need to make sure we round up.
86 */
87 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
Simon Glass1b2fd5b2015-09-01 19:19:37 -060088
Philipp Tomsich9fc354e2017-04-20 22:05:52 +020089 /* The baudrate register (BAUDR) is defined as a 32bit register where
90 * the upper 16bit are reserved and having 'Fsclk_out' in the lower
91 * 16bits with 'Fsclk_out' defined as follows:
92 *
93 * Fsclk_out = Fspi_clk/ SCKDV
94 * Where SCKDV is any even value between 2 and 65534.
95 */
96 if (clk_div > 0xfffe) {
97 clk_div = 0xfffe;
Heinrich Schuchardt11f12c12017-11-12 20:59:44 +010098 debug("%s: can't divide down to %d Hz (actual will be %d Hz)\n",
Philipp Tomsich9fc354e2017-04-20 22:05:52 +020099 __func__, speed, priv->input_rate / clk_div);
100 }
101
102 /* Round up to the next even 16bit number */
103 clk_div = (clk_div + 1) & 0xfffe;
104
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600105 debug("spi speed %u, div %u\n", speed, clk_div);
106
Philipp Tomsich9fc354e2017-04-20 22:05:52 +0200107 clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
Simon Glass28a943c2016-01-21 19:44:03 -0700108 priv->last_speed_hz = speed;
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600109}
110
111static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
112{
113 unsigned long start;
114
115 start = get_timer(0);
116 while (readl(&regs->sr) & SR_BUSY) {
117 if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
118 debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
119 return -ETIMEDOUT;
120 }
121 }
122
123 return 0;
124}
125
Simon Glass183a3a02016-01-21 19:44:10 -0700126static void spi_cs_activate(struct udevice *dev, uint cs)
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600127{
Simon Glass183a3a02016-01-21 19:44:10 -0700128 struct udevice *bus = dev->parent;
129 struct rockchip_spi_platdata *plat = bus->platdata;
130 struct rockchip_spi_priv *priv = dev_get_priv(bus);
131 struct rockchip_spi *regs = priv->regs;
132
Simon Glassb4252472016-11-13 14:22:03 -0700133 /* If it's too soon to do another transaction, wait */
134 if (plat->deactivate_delay_us && priv->last_transaction_us) {
135 ulong delay_us; /* The delay completed so far */
136 delay_us = timer_get_us() - priv->last_transaction_us;
Philipp Tomsichf92cf0a2019-02-03 16:17:26 +0100137 if (delay_us < plat->deactivate_delay_us) {
138 ulong additional_delay_us =
139 plat->deactivate_delay_us - delay_us;
140 debug("%s: delaying by %ld us\n",
141 __func__, additional_delay_us);
142 udelay(additional_delay_us);
143 }
Simon Glassb4252472016-11-13 14:22:03 -0700144 }
145
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600146 debug("activate cs%u\n", cs);
147 writel(1 << cs, &regs->ser);
Simon Glass183a3a02016-01-21 19:44:10 -0700148 if (plat->activate_delay_us)
149 udelay(plat->activate_delay_us);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600150}
151
Simon Glass183a3a02016-01-21 19:44:10 -0700152static void spi_cs_deactivate(struct udevice *dev, uint cs)
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600153{
Simon Glass183a3a02016-01-21 19:44:10 -0700154 struct udevice *bus = dev->parent;
155 struct rockchip_spi_platdata *plat = bus->platdata;
156 struct rockchip_spi_priv *priv = dev_get_priv(bus);
157 struct rockchip_spi *regs = priv->regs;
158
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600159 debug("deactivate cs%u\n", cs);
160 writel(0, &regs->ser);
Simon Glass183a3a02016-01-21 19:44:10 -0700161
162 /* Remember time of this transaction so we can honour the bus delay */
163 if (plat->deactivate_delay_us)
164 priv->last_transaction_us = timer_get_us();
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600165}
166
Simon Glass6e019c42016-11-13 14:22:02 -0700167#if CONFIG_IS_ENABLED(OF_PLATDATA)
168static int conv_of_platdata(struct udevice *dev)
169{
170 struct rockchip_spi_platdata *plat = dev->platdata;
171 struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat;
172 struct rockchip_spi_priv *priv = dev_get_priv(dev);
173 int ret;
174
175 plat->base = dtplat->reg[0];
176 plat->frequency = 20000000;
177 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
178 if (ret < 0)
179 return ret;
180 dev->req_seq = 0;
181
182 return 0;
183}
184#endif
185
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600186static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
187{
Simon Glass6e019c42016-11-13 14:22:02 -0700188#if !CONFIG_IS_ENABLED(OF_PLATDATA)
189 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
Simon Glass71037d12016-01-21 19:43:43 -0700190 struct rockchip_spi_priv *priv = dev_get_priv(bus);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600191 int ret;
192
Philipp Tomsichd27c2732017-09-11 22:04:20 +0200193 plat->base = dev_read_addr(bus);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600194
Simon Glass71037d12016-01-21 19:43:43 -0700195 ret = clk_get_by_index(bus, 0, &priv->clk);
196 if (ret < 0) {
197 debug("%s: Could not get clock for %s: %d\n", __func__,
198 bus->name, ret);
199 return ret;
200 }
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600201
Philipp Tomsich6c65577c2017-06-07 18:45:58 +0200202 plat->frequency =
203 dev_read_u32_default(bus, "spi-max-frequency", 50000000);
204 plat->deactivate_delay_us =
205 dev_read_u32_default(bus, "spi-deactivate-delay", 0);
206 plat->activate_delay_us =
207 dev_read_u32_default(bus, "spi-activate-delay", 0);
208
Simon Glass90a28472016-01-21 19:44:12 -0700209 debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n",
210 __func__, (uint)plat->base, plat->frequency,
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600211 plat->deactivate_delay_us);
Simon Glass6e019c42016-11-13 14:22:02 -0700212#endif
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600213
214 return 0;
215}
216
Philipp Tomsichbd376712017-04-20 22:05:51 +0200217static int rockchip_spi_calc_modclk(ulong max_freq)
218{
Philipp Tomsichd16120a2017-07-25 16:25:30 +0200219 /*
220 * While this is not strictly correct for the RK3368, as the
221 * GPLL will be 576MHz, things will still work, as the
222 * clk_set_rate(...) implementation in our clock-driver will
223 * chose the next closest rate not exceeding what we request
224 * based on the output of this function.
225 */
226
Philipp Tomsichbd376712017-04-20 22:05:51 +0200227 unsigned div;
228 const unsigned long gpll_hz = 594000000UL;
229
230 /*
231 * We need to find an input clock that provides at least twice
232 * the maximum frequency and can be generated from the assumed
233 * speed of GPLL (594MHz) using an integer divider.
234 *
235 * To give us more achievable bitrates at higher speeds (these
236 * are generated by dividing by an even 16-bit integer from
237 * this frequency), we try to have an input frequency of at
238 * least 4x our max_freq.
239 */
240
241 div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
242 return gpll_hz / div;
243}
244
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600245static int rockchip_spi_probe(struct udevice *bus)
246{
247 struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
248 struct rockchip_spi_priv *priv = dev_get_priv(bus);
249 int ret;
250
251 debug("%s: probe\n", __func__);
Simon Glass6e019c42016-11-13 14:22:02 -0700252#if CONFIG_IS_ENABLED(OF_PLATDATA)
253 ret = conv_of_platdata(bus);
254 if (ret)
255 return ret;
256#endif
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600257 priv->regs = (struct rockchip_spi *)plat->base;
258
259 priv->last_transaction_us = timer_get_us();
260 priv->max_freq = plat->frequency;
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600261
Philipp Tomsichbd376712017-04-20 22:05:51 +0200262 /* Clamp the value from the DTS against any hardware limits */
263 if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
264 priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
265
266 /* Find a module-input clock that fits with the max_freq setting */
267 ret = clk_set_rate(&priv->clk,
268 rockchip_spi_calc_modclk(priv->max_freq));
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600269 if (ret < 0) {
270 debug("%s: Failed to set clock: %d\n", __func__, ret);
271 return ret;
272 }
273 priv->input_rate = ret;
274 debug("%s: rate = %u\n", __func__, priv->input_rate);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600275
276 return 0;
277}
278
279static int rockchip_spi_claim_bus(struct udevice *dev)
280{
281 struct udevice *bus = dev->parent;
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600282 struct rockchip_spi_priv *priv = dev_get_priv(bus);
283 struct rockchip_spi *regs = priv->regs;
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600284 uint ctrlr0;
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600285
286 /* Disable the SPI hardware */
Philipp Tomsichb6101e92019-02-03 16:17:29 +0100287 rkspi_enable_chip(regs, false);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600288
Simon Glass28a943c2016-01-21 19:44:03 -0700289 if (priv->speed_hz != priv->last_speed_hz)
290 rkspi_set_clk(priv, priv->speed_hz);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600291
292 /* Operation Mode */
293 ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
294
295 /* Data Frame Size */
Philipp Tomsich0e661b62019-02-03 16:17:27 +0100296 ctrlr0 |= DFS_8BIT << DFS_SHIFT;
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600297
298 /* set SPI mode 0..3 */
299 if (priv->mode & SPI_CPOL)
300 ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
301 if (priv->mode & SPI_CPHA)
302 ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
303
304 /* Chip Select Mode */
305 ctrlr0 |= CSM_KEEP << CSM_SHIFT;
306
307 /* SSN to Sclk_out delay */
308 ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
309
310 /* Serial Endian Mode */
311 ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
312
313 /* First Bit Mode */
314 ctrlr0 |= FBM_MSB << FBM_SHIFT;
315
316 /* Byte and Halfword Transform */
Philipp Tomsich0e661b62019-02-03 16:17:27 +0100317 ctrlr0 |= HALF_WORD_OFF << HALF_WORD_TX_SHIFT;
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600318
319 /* Rxd Sample Delay */
320 ctrlr0 |= 0 << RXDSD_SHIFT;
321
322 /* Frame Format */
323 ctrlr0 |= FRF_SPI << FRF_SHIFT;
324
325 /* Tx and Rx mode */
Philipp Tomsich0e661b62019-02-03 16:17:27 +0100326 ctrlr0 |= TMOD_TR << TMOD_SHIFT;
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600327
328 writel(ctrlr0, &regs->ctrlr0);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600329
330 return 0;
331}
332
333static int rockchip_spi_release_bus(struct udevice *dev)
334{
Simon Glasse15af8e2016-01-21 19:44:11 -0700335 struct udevice *bus = dev->parent;
336 struct rockchip_spi_priv *priv = dev_get_priv(bus);
337
338 rkspi_enable_chip(priv->regs, false);
339
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600340 return 0;
341}
342
Philipp Tomsich8aa6c922019-02-03 16:17:31 +0100343static inline int rockchip_spi_16bit_reader(struct udevice *dev,
344 u8 **din, int *len)
345{
346 struct udevice *bus = dev->parent;
347 const struct rockchip_spi_params * const data =
348 (void *)dev_get_driver_data(bus);
349 struct rockchip_spi_priv *priv = dev_get_priv(bus);
350 struct rockchip_spi *regs = priv->regs;
351 const u32 saved_ctrlr0 = readl(&regs->ctrlr0);
352#if defined(DEBUG)
353 u32 statistics_rxlevels[33] = { };
354#endif
355 u32 frames = *len / 2;
Philipp Tomsich22361492019-02-03 16:17:33 +0100356 u8 *in = (u8 *)(*din);
Philipp Tomsich8aa6c922019-02-03 16:17:31 +0100357 u32 max_chunk_size = SPI_FIFO_DEPTH;
358
359 if (!frames)
360 return 0;
361
362 /*
Philipp Tomsich51a644a2019-02-03 16:17:32 +0100363 * If we know that the hardware will manage RXFIFO overruns
364 * (i.e. stop the SPI clock until there's space in the FIFO),
365 * we the allow largest possible chunk size that can be
366 * represented in CTRLR1.
367 */
368 if (data && data->master_manages_fifo)
369 max_chunk_size = 0x10000;
370
Philipp Tomsich8aa6c922019-02-03 16:17:31 +0100371 // rockchip_spi_configure(dev, mode, size)
372 rkspi_enable_chip(regs, false);
373 clrsetbits_le32(&regs->ctrlr0,
374 TMOD_MASK << TMOD_SHIFT,
375 TMOD_RO << TMOD_SHIFT);
376 /* 16bit data frame size */
377 clrsetbits_le32(&regs->ctrlr0, DFS_MASK, DFS_16BIT);
378
379 /* Update caller's context */
380 const u32 bytes_to_process = 2 * frames;
381 *din += bytes_to_process;
382 *len -= bytes_to_process;
383
384 /* Process our frames */
385 while (frames) {
386 u32 chunk_size = min(frames, max_chunk_size);
387
388 frames -= chunk_size;
389
390 writew(chunk_size - 1, &regs->ctrlr1);
391 rkspi_enable_chip(regs, true);
392
393 do {
394 u32 rx_level = readw(&regs->rxflr);
395#if defined(DEBUG)
396 statistics_rxlevels[rx_level]++;
397#endif
398 chunk_size -= rx_level;
Philipp Tomsich22361492019-02-03 16:17:33 +0100399 while (rx_level--) {
400 u16 val = readw(regs->rxdr);
401 *in++ = val & 0xff;
402 *in++ = val >> 8;
403 }
Philipp Tomsich8aa6c922019-02-03 16:17:31 +0100404 } while (chunk_size);
405
406 rkspi_enable_chip(regs, false);
407 }
408
409#if defined(DEBUG)
410 debug("%s: observed rx_level during processing:\n", __func__);
411 for (int i = 0; i <= 32; ++i)
412 if (statistics_rxlevels[i])
413 debug("\t%2d: %d\n", i, statistics_rxlevels[i]);
414#endif
415 /* Restore the original transfer setup and return error-free. */
416 writel(saved_ctrlr0, &regs->ctrlr0);
417 return 0;
418}
419
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600420static int rockchip_spi_xfer(struct udevice *dev, unsigned int bitlen,
421 const void *dout, void *din, unsigned long flags)
422{
423 struct udevice *bus = dev->parent;
424 struct rockchip_spi_priv *priv = dev_get_priv(bus);
425 struct rockchip_spi *regs = priv->regs;
426 struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
427 int len = bitlen >> 3;
428 const u8 *out = dout;
429 u8 *in = din;
430 int toread, towrite;
Philipp Tomsich8aa6c922019-02-03 16:17:31 +0100431 int ret = 0;
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600432
433 debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
434 len, flags);
435 if (DEBUG_RK_SPI)
436 rkspi_dump_regs(regs);
437
438 /* Assert CS before transfer */
439 if (flags & SPI_XFER_BEGIN)
Simon Glass183a3a02016-01-21 19:44:10 -0700440 spi_cs_activate(dev, slave_plat->cs);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600441
Philipp Tomsich8aa6c922019-02-03 16:17:31 +0100442 /*
443 * To ensure fast loading of firmware images (e.g. full U-Boot
444 * stage, ATF, Linux kernel) from SPI flash, we optimise the
445 * case of read-only transfers by using the full 16bits of each
446 * FIFO element.
447 */
448 if (!out)
449 ret = rockchip_spi_16bit_reader(dev, &in, &len);
450
451 /* This is the original 8bit reader/writer code */
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600452 while (len > 0) {
Philipp Tomsiche647dec2019-02-03 16:17:28 +0100453 int todo = min(len, 0x10000);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600454
Simon Glasse15af8e2016-01-21 19:44:11 -0700455 rkspi_enable_chip(regs, false);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600456 writel(todo - 1, &regs->ctrlr1);
457 rkspi_enable_chip(regs, true);
458
459 toread = todo;
460 towrite = todo;
461 while (toread || towrite) {
462 u32 status = readl(&regs->sr);
463
464 if (towrite && !(status & SR_TF_FULL)) {
465 writel(out ? *out++ : 0, regs->txdr);
466 towrite--;
467 }
468 if (toread && !(status & SR_RF_EMPT)) {
469 u32 byte = readl(regs->rxdr);
470
471 if (in)
472 *in++ = byte;
473 toread--;
474 }
475 }
Philipp Tomsich7e0e5c52019-02-03 16:17:30 +0100476
477 /*
478 * In case that there's a transmit-component, we need to wait
479 * until the control goes idle before we can disable the SPI
480 * control logic (as this will implictly flush the FIFOs).
481 */
482 if (out) {
483 ret = rkspi_wait_till_not_busy(regs);
484 if (ret)
485 break;
486 }
487
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600488 len -= todo;
489 }
490
491 /* Deassert CS after transfer */
492 if (flags & SPI_XFER_END)
Simon Glass183a3a02016-01-21 19:44:10 -0700493 spi_cs_deactivate(dev, slave_plat->cs);
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600494
495 rkspi_enable_chip(regs, false);
496
497 return ret;
498}
499
500static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
501{
502 struct rockchip_spi_priv *priv = dev_get_priv(bus);
503
Philipp Tomsichbd376712017-04-20 22:05:51 +0200504 /* Clamp to the maximum frequency specified in the DTS */
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600505 if (speed > priv->max_freq)
506 speed = priv->max_freq;
Philipp Tomsichbd376712017-04-20 22:05:51 +0200507
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600508 priv->speed_hz = speed;
509
510 return 0;
511}
512
513static int rockchip_spi_set_mode(struct udevice *bus, uint mode)
514{
515 struct rockchip_spi_priv *priv = dev_get_priv(bus);
516
517 priv->mode = mode;
518
519 return 0;
520}
521
522static const struct dm_spi_ops rockchip_spi_ops = {
523 .claim_bus = rockchip_spi_claim_bus,
524 .release_bus = rockchip_spi_release_bus,
525 .xfer = rockchip_spi_xfer,
526 .set_speed = rockchip_spi_set_speed,
527 .set_mode = rockchip_spi_set_mode,
528 /*
529 * cs_info is not needed, since we require all chip selects to be
530 * in the device tree explicitly
531 */
532};
533
Philipp Tomsich51a644a2019-02-03 16:17:32 +0100534const struct rockchip_spi_params rk3399_spi_params = {
535 .master_manages_fifo = true,
536};
537
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600538static const struct udevice_id rockchip_spi_ids[] = {
539 { .compatible = "rockchip,rk3288-spi" },
Philipp Tomsich51a644a2019-02-03 16:17:32 +0100540 { .compatible = "rockchip,rk3368-spi",
541 .data = (ulong)&rk3399_spi_params },
542 { .compatible = "rockchip,rk3399-spi",
543 .data = (ulong)&rk3399_spi_params },
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600544 { }
545};
546
547U_BOOT_DRIVER(rockchip_spi) = {
Simon Glass6e019c42016-11-13 14:22:02 -0700548#if CONFIG_IS_ENABLED(OF_PLATDATA)
549 .name = "rockchip_rk3288_spi",
550#else
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600551 .name = "rockchip_spi",
Simon Glass6e019c42016-11-13 14:22:02 -0700552#endif
Simon Glass1b2fd5b2015-09-01 19:19:37 -0600553 .id = UCLASS_SPI,
554 .of_match = rockchip_spi_ids,
555 .ops = &rockchip_spi_ops,
556 .ofdata_to_platdata = rockchip_spi_ofdata_to_platdata,
557 .platdata_auto_alloc_size = sizeof(struct rockchip_spi_platdata),
558 .priv_auto_alloc_size = sizeof(struct rockchip_spi_priv),
559 .probe = rockchip_spi_probe,
560};