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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
TsiChungLiew1ac559d2008-01-14 17:19:54 -06002/*
3 * (C) Copyright 2000-2003
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
Alison Wangaa0d99f2012-03-26 21:49:05 +00006 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChungLiew1ac559d2008-01-14 17:19:54 -06007 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiew1ac559d2008-01-14 17:19:54 -06008 */
9
10#include <config.h>
11#include <common.h>
12#include <asm/immap.h>
Alison Wangaa0d99f2012-03-26 21:49:05 +000013#include <asm/io.h>
TsiChungLiew1ac559d2008-01-14 17:19:54 -060014
15DECLARE_GLOBAL_DATA_PTR;
16
17int checkboard(void)
18{
19 puts("Board: ");
20 puts("Freescale FireEngine 5373 EVB\n");
21 return 0;
22};
23
Simon Glassf1683aa2017-04-06 12:47:05 -060024int dram_init(void)
TsiChungLiew1ac559d2008-01-14 17:19:54 -060025{
Alison Wangaa0d99f2012-03-26 21:49:05 +000026 sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
TsiChungLiew1ac559d2008-01-14 17:19:54 -060027 u32 dramsize, i;
28
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
TsiChungLiew1ac559d2008-01-14 17:19:54 -060030
31 for (i = 0x13; i < 0x20; i++) {
32 if (dramsize == (1 << i))
33 break;
34 }
35 i--;
36
Alison Wangaa0d99f2012-03-26 21:49:05 +000037 out_be32(&sdram->cs0, CONFIG_SYS_SDRAM_BASE | i);
38 out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
39 out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
TsiChungLiew1ac559d2008-01-14 17:19:54 -060040
41 /* Issue PALL */
Alison Wangaa0d99f2012-03-26 21:49:05 +000042 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
TsiChungLiew1ac559d2008-01-14 17:19:54 -060043
44 /* Issue LEMR */
Alison Wangaa0d99f2012-03-26 21:49:05 +000045 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
46 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
TsiChungLiew1ac559d2008-01-14 17:19:54 -060047
48 udelay(500);
49
50 /* Issue PALL */
Alison Wangaa0d99f2012-03-26 21:49:05 +000051 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
TsiChungLiew1ac559d2008-01-14 17:19:54 -060052
53 /* Perform two refresh cycles */
Alison Wangaa0d99f2012-03-26 21:49:05 +000054 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
55 out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
TsiChungLiew1ac559d2008-01-14 17:19:54 -060056
Alison Wangaa0d99f2012-03-26 21:49:05 +000057 out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
TsiChungLiew1ac559d2008-01-14 17:19:54 -060058
Alison Wangaa0d99f2012-03-26 21:49:05 +000059 out_be32(&sdram->ctrl,
60 (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
TsiChungLiew1ac559d2008-01-14 17:19:54 -060061
62 udelay(100);
63
Simon Glass088454c2017-03-31 08:40:25 -060064 gd->ram_size = dramsize;
65
66 return 0;
TsiChungLiew1ac559d2008-01-14 17:19:54 -060067};
68
69int testdram(void)
70{
71 /* TODO: XXX XXX XXX */
72 printf("DRAM test not implemented!\n");
73
74 return (0);
75}