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Steve Sakoman3e76d622010-06-08 13:07:46 -07001/*
2 * (C) Copyright 2010
3 * Texas Instruments Incorporated.
4 * Aneesh V <aneesh@ti.com>
5 * Steve Sakoman <steve@sakoman.com>
6 *
7 * Configuration settings for the TI SDP4430 board.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 */
34#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
35#define CONFIG_OMAP 1 /* in a TI OMAP core */
36#define CONFIG_OMAP44XX 1 /* which is a 44XX */
37#define CONFIG_OMAP4430 1 /* which is in a 4430 */
38#define CONFIG_4430SDP 1 /* working with SDP */
Steve Sakoman2ad853c2010-07-15 13:43:10 -070039#define CONFIG_ARCH_CPU_INIT
Steve Sakoman3e76d622010-06-08 13:07:46 -070040
41/* Get CPU defs */
42#include <asm/arch/cpu.h>
43#include <asm/arch/omap4.h>
44
45/* Display CPU and Board Info */
46#define CONFIG_DISPLAY_CPUINFO 1
47#define CONFIG_DISPLAY_BOARDINFO 1
48
Steve Sakoman3e76d622010-06-08 13:07:46 -070049/* Clock Defines */
50#define V_OSCK 38400000 /* Clock output from T2 */
51#define V_SCLK V_OSCK
52
53#undef CONFIG_USE_IRQ /* no support for IRQs */
54#define CONFIG_MISC_INIT_R
55
Grant Likely2fa8ca92011-03-28 09:59:07 +000056#define CONFIG_OF_LIBFDT 1
57
Steve Sakoman3e76d622010-06-08 13:07:46 -070058#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
59#define CONFIG_SETUP_MEMORY_TAGS 1
60#define CONFIG_INITRD_TAG 1
61#define CONFIG_REVISION_TAG 1
62
63/*
64 * Size of malloc() pool
Sukumar Ghorai64455352010-09-14 13:52:34 +053065 * Total Size Environment - 128k
Steve Sakoman3e76d622010-06-08 13:07:46 -070066 * Malloc - add 256k
67 */
Sukumar Ghorai64455352010-09-14 13:52:34 +053068#define CONFIG_ENV_SIZE (128 << 10)
Steve Sakoman3e76d622010-06-08 13:07:46 -070069#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10))
Steve Sakoman3e76d622010-06-08 13:07:46 -070070/* Vector Base */
71#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE
72
73/*
74 * Hardware drivers
75 */
76
77/*
78 * serial port - NS16550 compatible
79 */
80#define V_NS16550_CLK 48000000
81
82#define CONFIG_SYS_NS16550
83#define CONFIG_SYS_NS16550_SERIAL
84#define CONFIG_SYS_NS16550_REG_SIZE (-4)
85#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
86#define CONFIG_CONS_INDEX 3
87#define CONFIG_SYS_NS16550_COM3 UART3_BASE
88
Steve Sakoman3e76d622010-06-08 13:07:46 -070089#define CONFIG_BAUDRATE 115200
90#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
91 115200}
Steve Sakoman3e76d622010-06-08 13:07:46 -070092/* I2C */
93#define CONFIG_HARD_I2C 1
94#define CONFIG_SYS_I2C_SPEED 100000
95#define CONFIG_SYS_I2C_SLAVE 1
96#define CONFIG_SYS_I2C_BUS 0
97#define CONFIG_SYS_I2C_BUS_SELECT 1
98#define CONFIG_DRIVER_OMAP34XX_I2C 1
99#define CONFIG_I2C_MULTI_BUS 1
100
Steve Sakoman516799f2010-07-15 12:53:42 -0700101/* TWL6030 */
102#define CONFIG_TWL6030_POWER 1
Balaji T K3e664f62010-11-25 16:22:04 +0530103#define CONFIG_CMD_BAT 1
Steve Sakoman516799f2010-07-15 12:53:42 -0700104
Steve Sakoman3e76d622010-06-08 13:07:46 -0700105/* MMC */
Sukumar Ghorai084c4c12010-09-18 20:59:54 -0700106#define CONFIG_GENERIC_MMC 1
Steve Sakoman3e76d622010-06-08 13:07:46 -0700107#define CONFIG_MMC 1
Sukumar Ghorai084c4c12010-09-18 20:59:54 -0700108#define CONFIG_OMAP_HSMMC 1
Steve Sakoman3e76d622010-06-08 13:07:46 -0700109#define CONFIG_SYS_MMC_SET_DEV 1
110#define CONFIG_DOS_PARTITION 1
111
Sukumar Ghorai64455352010-09-14 13:52:34 +0530112/* MMC ENV related defines */
113#define CONFIG_ENV_IS_IN_MMC 1
114#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
115#define CONFIG_ENV_OFFSET 0xE0000
116
Steve Sakoman325abab2010-06-25 12:44:33 -0700117/* USB */
118#define CONFIG_MUSB_UDC 1
119#define CONFIG_USB_OMAP3 1
120
121/* USB device configuration */
122#define CONFIG_USB_DEVICE 1
123#define CONFIG_USB_TTY 1
124#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
Steve Sakoman325abab2010-06-25 12:44:33 -0700125
Steve Sakoman3e76d622010-06-08 13:07:46 -0700126/* Flash */
127#define CONFIG_SYS_NO_FLASH 1
128
129/* commands to include */
130#include <config_cmd_default.h>
131
132/* Enabled commands */
133#define CONFIG_CMD_EXT2 /* EXT2 Support */
134#define CONFIG_CMD_FAT /* FAT support */
135#define CONFIG_CMD_I2C /* I2C serial bus support */
136#define CONFIG_CMD_MMC /* MMC support */
Sukumar Ghorai64455352010-09-14 13:52:34 +0530137#define CONFIG_CMD_SAVEENV
Steve Sakoman3e76d622010-06-08 13:07:46 -0700138
139/* Disabled commands */
140#undef CONFIG_CMD_NET
Dirk Behme35cf8842010-11-28 20:00:12 -0500141#undef CONFIG_CMD_NFS
Steve Sakoman3e76d622010-06-08 13:07:46 -0700142#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
143#undef CONFIG_CMD_IMLS /* List all found images */
144
145/*
Steve Sakoman3e76d622010-06-08 13:07:46 -0700146 * Environment setup
147 */
148
Steve Sakoman1b03eed2010-07-07 15:25:25 -0700149#define CONFIG_BOOTDELAY 3
150
Steve Sakoman3e76d622010-06-08 13:07:46 -0700151#define CONFIG_ENV_OVERWRITE
152
153#define CONFIG_EXTRA_ENV_SETTINGS \
154 "loadaddr=0x82000000\0" \
155 "console=ttyS2,115200n8\0" \
Steve Sakoman325abab2010-06-25 12:44:33 -0700156 "usbtty=cdc_acm\0" \
Steve Sakoman1b03eed2010-07-07 15:25:25 -0700157 "vram=16M\0" \
Sukumar Ghorai084c4c12010-09-18 20:59:54 -0700158 "mmcdev=0\0" \
Steve Sakoman3e76d622010-06-08 13:07:46 -0700159 "mmcroot=/dev/mmcblk0p2 rw\0" \
160 "mmcrootfstype=ext3 rootwait\0" \
161 "mmcargs=setenv bootargs console=${console} " \
Steve Sakoman1b03eed2010-07-07 15:25:25 -0700162 "vram=${vram} " \
Steve Sakoman3e76d622010-06-08 13:07:46 -0700163 "root=${mmcroot} " \
164 "rootfstype=${mmcrootfstype}\0" \
165 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
166 "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \
167 "source ${loadaddr}\0" \
168 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
169 "mmcboot=echo Booting from mmc${mmcdev} ...; " \
170 "run mmcargs; " \
171 "bootm ${loadaddr}\0" \
172
173#define CONFIG_BOOTCOMMAND \
Sukumar Ghorai084c4c12010-09-18 20:59:54 -0700174 "if mmc rescan ${mmcdev}; then " \
Steve Sakoman3e76d622010-06-08 13:07:46 -0700175 "if run loadbootscript; then " \
176 "run bootscript; " \
177 "else " \
178 "if run loaduimage; then " \
179 "run mmcboot; " \
Steve Sakoman3e76d622010-06-08 13:07:46 -0700180 "fi; " \
181 "fi; " \
182 "fi"
183
184#define CONFIG_AUTO_COMPLETE 1
185
186/*
187 * Miscellaneous configurable options
188 */
189
190#define CONFIG_SYS_LONGHELP /* undef to save memory */
191#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
192#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
193#define CONFIG_SYS_PROMPT "OMAP4430 SDP # "
194#define CONFIG_SYS_CBSIZE 256
195/* Print Buffer Size */
196#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
197 sizeof(CONFIG_SYS_PROMPT) + 16)
198#define CONFIG_SYS_MAXARGS 16
199/* Boot Argument Buffer Size */
200#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
201
202/*
203 * memtest setup
204 */
205#define CONFIG_SYS_MEMTEST_START 0x80000000
206#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20))
207
208/* Default load address */
209#define CONFIG_SYS_LOAD_ADDR 0x80000000
210
211/* Use General purpose timer 1 */
Steve Sakoman674e0b22010-07-20 14:56:07 -0700212#define CONFIG_SYS_TIMERBASE GPT2_BASE
Steve Sakoman3e76d622010-06-08 13:07:46 -0700213#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
214#define CONFIG_SYS_HZ 1000
215
216/*
217 * Stack sizes
218 *
219 * The stack sizes are set up in start.S using the settings below
220 */
221#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */
222#ifdef CONFIG_USE_IRQ
223#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */
224#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */
225#endif
226
227/*
228 * SDRAM Memory Map
229 * Even though we use two CS all the memory
230 * is mapped to one contiguous block
231 */
232#define CONFIG_NR_DRAM_BANKS 1
233
Steve Sakoman57b512b2010-09-29 20:59:51 -0700234#define CONFIG_SYS_SDRAM_BASE 0x80000000
Steve Sakoman31bfcf12010-10-27 05:04:30 -0700235#define CONFIG_SYS_INIT_RAM_ADDR 0x4030D800
236#define CONFIG_SYS_INIT_RAM_SIZE 0x800
237#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
238 CONFIG_SYS_INIT_RAM_SIZE - \
239 GENERATED_GBL_DATA_SIZE)
Steve Sakoman57b512b2010-09-29 20:59:51 -0700240
Aneesh V8b457fa2011-06-16 23:30:52 +0000241#ifndef CONFIG_SYS_L2CACHE_OFF
242#define CONFIG_SYS_L2_PL310 1
243#define CONFIG_SYS_PL310_BASE 0x48242000
244#endif
245
Aneesh V095aea22011-07-21 09:10:12 -0400246/* Defines for SDRAM init */
247#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
Aneesh V1e463862011-07-21 09:10:15 -0400248#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
Aneesh V095aea22011-07-21 09:10:12 -0400249#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
250#endif
251
Aneesh Vbcae7212011-07-21 09:10:21 -0400252/* Defines for SPL */
253#define CONFIG_SPL
254#define CONFIG_SPL_TEXT_BASE 0x40304350
255#define CONFIG_SPL_MAX_SIZE 0x8000 /* 32 K */
256#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
257
258#define CONFIG_SPL_BSS_START_ADDR 0x80000000
259#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
260
261#define CONFIG_SPL_LIBCOMMON_SUPPORT
262#define CONFIG_SPL_LIBDISK_SUPPORT
263#define CONFIG_SPL_I2C_SUPPORT
264#define CONFIG_SPL_MMC_SUPPORT
265#define CONFIG_SPL_FAT_SUPPORT
266#define CONFIG_SPL_LIBGENERIC_SUPPORT
267#define CONFIG_SPL_SERIAL_SUPPORT
268#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
269
270/*
271 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
272 * 64 bytes before this address should be set aside for u-boot.img's
273 * header. That is 0x800FFFC0--0x80100000 should not be used for any
274 * other needs.
275 */
276#define CONFIG_SYS_TEXT_BASE 0x80100000
277
Steve Sakoman3e76d622010-06-08 13:07:46 -0700278#endif /* __CONFIG_H */