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Gabe Blackef5a5b02011-11-29 18:05:07 +00001/*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 * (C) Copyright 2008
4 * Graeme Russ, graeme.russ@gmail.com.
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
Gabe Blackef5a5b02011-11-29 18:05:07 +00007 */
8
9#include <asm/ibmpc.h>
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
21#define CONFIG_SYS_COREBOOT
Stefan Reinauer300081a2012-12-03 13:58:12 +000022#define CONFIG_SHOW_BOOT_PROGRESS
Gabe Blackef5a5b02011-11-29 18:05:07 +000023#define CONFIG_LAST_STAGE_INIT
Simon Glassa78d4942012-10-20 12:33:15 +000024#define CONFIG_SYS_VSNPRINTF
Simon Glass34d60572012-12-02 04:49:55 +000025#define CONFIG_ZBOOT_32
Simon Glassac426b72012-12-05 15:11:27 +000026#define CONFIG_PHYSMEM
Simon Glass617c2462013-04-15 11:25:21 +000027#define CONFIG_SYS_EARLY_PCI_INIT
Gabe Blackef5a5b02011-11-29 18:05:07 +000028
Simon Glassfc959082013-02-28 19:26:18 +000029#define CONFIG_LMB
30#define CONFIG_OF_LIBFDT
31#define CONFIG_OF_CONTROL
32#define CONFIG_OF_SEPARATE
33#define CONFIG_DEFAULT_DEVICE_TREE link
34
Simon Glass2e659592013-04-17 16:13:43 +000035#define CONFIG_BOOTSTAGE
36#define CONFIG_BOOTSTAGE_REPORT
37#define CONFIG_BOOTSTAGE_FDT
38#define CONFIG_CMD_BOOTSTAGE
39/* Place to stash bootstage data from first-stage U-Boot */
40#define CONFIG_BOOTSTAGE_STASH 0x0110f000
41#define CONFIG_BOOTSTAGE_STASH_SIZE 0x7fc
42#define CONFIG_BOOTSTAGE_USER_COUNT 60
43
Simon Glass04dbf772013-04-17 16:13:46 +000044#define CONFIG_LZO
45#undef CONFIG_ZLIB
46#undef CONFIG_GZIP
47
Gabe Blackef5a5b02011-11-29 18:05:07 +000048/*-----------------------------------------------------------------------
49 * Watchdog Configuration
50 */
51#undef CONFIG_WATCHDOG
52#undef CONFIG_HW_WATCHDOG
53
Simon Glass51bdad62012-10-29 05:24:05 +000054/* SATA AHCI storage */
55
56#define CONFIG_SCSI_AHCI
57
58#ifdef CONFIG_SCSI_AHCI
Rob Herring344ca0b2013-08-24 10:10:54 -050059#define CONFIG_LIBATA
Simon Glass51bdad62012-10-29 05:24:05 +000060#define CONFIG_SYS_64BIT_LBA
61#define CONFIG_SATA_INTEL 1
62#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
63 PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
64 {PCI_VENDOR_ID_INTEL, \
65 PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
66 {PCI_VENDOR_ID_INTEL, \
67 PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
68 {PCI_VENDOR_ID_INTEL, \
69 PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
70
71#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
72#define CONFIG_SYS_SCSI_MAX_LUN 1
73#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
74 CONFIG_SYS_SCSI_MAX_LUN)
75#endif
76
Simon Glassd02a5682012-11-25 20:12:16 +000077/* Generic TPM interfaced through LPC bus */
Tom Wai-Hong Tam5bdf46b2013-04-12 11:04:35 +000078#define CONFIG_TPM
79#define CONFIG_TPM_TIS_LPC
Simon Glassd02a5682012-11-25 20:12:16 +000080#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000
81
Gabe Blackef5a5b02011-11-29 18:05:07 +000082/*-----------------------------------------------------------------------
83 * Real Time Clock Configuration
84 */
85#define CONFIG_RTC_MC146818
86#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
Simon Glasscbca8832012-11-03 11:41:42 +000087#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS
Gabe Blackef5a5b02011-11-29 18:05:07 +000088
89/*-----------------------------------------------------------------------
90 * Serial Configuration
91 */
Gabe Blackef5a5b02011-11-29 18:05:07 +000092#define CONFIG_CONS_INDEX 1
93#define CONFIG_SYS_NS16550
94#define CONFIG_SYS_NS16550_SERIAL
95#define CONFIG_SYS_NS16550_REG_SIZE 1
96#define CONFIG_SYS_NS16550_CLK 1843200
97#define CONFIG_BAUDRATE 9600
98#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
99 9600, 19200, 38400, 115200}
100#define CONFIG_SYS_NS16550_COM1 UART0_BASE
101#define CONFIG_SYS_NS16550_COM2 UART1_BASE
102#define CONFIG_SYS_NS16550_PORT_MAPPED
103
Simon Glass420a2ca2012-11-29 09:58:58 +0000104#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,eserial0\0" \
105 "stdout=vga,eserial0,cbmem\0" \
106 "stderr=vga,eserial0,cbmem\0"
107
108#define CONFIG_CONSOLE_MUX
109#define CONFIG_SYS_CONSOLE_IS_IN_ENV
110#define CONFIG_SYS_STDIO_DEREGISTER
111#define CONFIG_CBMEM_CONSOLE
112
Simon Glassac426b72012-12-05 15:11:27 +0000113#define CONFIG_CMDLINE_EDITING
114#define CONFIG_COMMAND_HISTORY
115#define CONFIG_AUTOCOMPLETE
Gabe Blackef5a5b02011-11-29 18:05:07 +0000116
117#define CONFIG_SUPPORT_VFAT
118/************************************************************
119 * ATAPI support (experimental)
120 ************************************************************/
121#define CONFIG_ATAPI
122
123/************************************************************
124 * DISK Partition support
125 ************************************************************/
Gabe Blackd954a432012-12-05 15:10:58 +0000126#define CONFIG_EFI_PARTITION
Gabe Blackef5a5b02011-11-29 18:05:07 +0000127#define CONFIG_DOS_PARTITION
128#define CONFIG_MAC_PARTITION
129#define CONFIG_ISO_PARTITION /* Experimental */
130
Gabe Blackd954a432012-12-05 15:10:58 +0000131#define CONFIG_CMD_PART
Simon Glassaf9f8812012-10-12 14:26:12 +0000132#define CONFIG_CMD_CBFS
133#define CONFIG_CMD_EXT4
134#define CONFIG_CMD_EXT4_WRITE
Gabe Blackd954a432012-12-05 15:10:58 +0000135#define CONFIG_PARTITION_UUIDS
Gabe Blackef5a5b02011-11-29 18:05:07 +0000136
137/*-----------------------------------------------------------------------
138 * Video Configuration
139 */
Simon Glasscbca8832012-11-03 11:41:42 +0000140#define CONFIG_VIDEO
141#define CONFIG_VIDEO_COREBOOT
142#define CONFIG_VIDEO_SW_CURSOR
143#define VIDEO_FB_16BPP_WORD_SWAP
144#define CONFIG_I8042_KBD
145#define CONFIG_CFB_CONSOLE
146#define CONFIG_SYS_CONSOLE_INFO_QUIET
Gabe Blackef5a5b02011-11-29 18:05:07 +0000147
Simon Glassa7e6d542012-12-02 03:44:44 +0000148/* x86 GPIOs are accessed through a PCI device */
149#define CONFIG_INTEL_ICH6_GPIO
150
Gabe Blackef5a5b02011-11-29 18:05:07 +0000151/*-----------------------------------------------------------------------
152 * Command line configuration.
153 */
154#include <config_cmd_default.h>
155
Simon Glassb5f31932013-06-11 11:14:53 -0700156#define CONFIG_TRACE
157#define CONFIG_CMD_TRACE
158#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
159#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
160#define CONFIG_TRACE_EARLY
161#define CONFIG_TRACE_EARLY_ADDR 0x01400000
162
Gabe Blackef5a5b02011-11-29 18:05:07 +0000163#define CONFIG_CMD_BDI
164#define CONFIG_CMD_BOOTD
165#define CONFIG_CMD_CONSOLE
166#define CONFIG_CMD_DATE
167#define CONFIG_CMD_ECHO
168#undef CONFIG_CMD_FLASH
169#define CONFIG_CMD_FPGA
Simon Glassa7e6d542012-12-02 03:44:44 +0000170#define CONFIG_CMD_GPIO
Gabe Blackef5a5b02011-11-29 18:05:07 +0000171#define CONFIG_CMD_IMI
172#undef CONFIG_CMD_IMLS
Simon Glassa08afb32012-12-14 13:05:17 +0000173#define CONFIG_CMD_IO
Gabe Blackef5a5b02011-11-29 18:05:07 +0000174#define CONFIG_CMD_IRQ
175#define CONFIG_CMD_ITEST
176#define CONFIG_CMD_LOADB
177#define CONFIG_CMD_LOADS
178#define CONFIG_CMD_MEMORY
179#define CONFIG_CMD_MISC
180#define CONFIG_CMD_NET
181#undef CONFIG_CMD_NFS
182#define CONFIG_CMD_PCI
183#define CONFIG_CMD_PING
184#define CONFIG_CMD_RUN
185#define CONFIG_CMD_SAVEENV
186#define CONFIG_CMD_SETGETDCR
187#define CONFIG_CMD_SOURCE
Simon Glass363464f2013-03-11 06:08:12 +0000188#define CONFIG_CMD_TIME
189#define CONFIG_CMD_GETTIME
Gabe Blackef5a5b02011-11-29 18:05:07 +0000190#define CONFIG_CMD_XIMG
Simon Glassac426b72012-12-05 15:11:27 +0000191#define CONFIG_CMD_SCSI
192
Gabe Blackef5a5b02011-11-29 18:05:07 +0000193#define CONFIG_CMD_FAT
194#define CONFIG_CMD_EXT2
195
Simon Glass34d60572012-12-02 04:49:55 +0000196#define CONFIG_CMD_ZBOOT
197
Gabe Blackef5a5b02011-11-29 18:05:07 +0000198#define CONFIG_BOOTDELAY 2
Simon Glassac426b72012-12-05 15:11:27 +0000199#define CONFIG_BOOTARGS \
200 "root=/dev/sdb3 init=/sbin/init rootwait ro"
201#define CONFIG_BOOTCOMMAND \
202 "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
203
Gabe Blackef5a5b02011-11-29 18:05:07 +0000204
205#if defined(CONFIG_CMD_KGDB)
206#define CONFIG_KGDB_BAUDRATE 115200
Gabe Blackef5a5b02011-11-29 18:05:07 +0000207#endif
208
209/*
210 * Miscellaneous configurable options
211 */
212#define CONFIG_SYS_LONGHELP
213#define CONFIG_SYS_PROMPT "boot > "
214#define CONFIG_SYS_CBSIZE 256
215#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
216 sizeof(CONFIG_SYS_PROMPT) + \
217 16)
218#define CONFIG_SYS_MAXARGS 16
219#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
220
221#define CONFIG_SYS_MEMTEST_START 0x00100000
222#define CONFIG_SYS_MEMTEST_END 0x01000000
223#define CONFIG_SYS_LOAD_ADDR 0x100000
Gabe Blackef5a5b02011-11-29 18:05:07 +0000224
225/*-----------------------------------------------------------------------
226 * SDRAM Configuration
227 */
228#define CONFIG_NR_DRAM_BANKS 4
229
230/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
231#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
232#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
233#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
234#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
235
236/*-----------------------------------------------------------------------
237 * CPU Features
238 */
239
Simon Glasse761ecd2013-04-17 16:13:36 +0000240#define CONFIG_SYS_X86_TSC_TIMER
Gabe Blackef5a5b02011-11-29 18:05:07 +0000241#define CONFIG_SYS_PCAT_INTERRUPTS
Simon Glassd0b6f242013-04-17 16:13:39 +0000242#define CONFIG_SYS_PCAT_TIMER
Gabe Blackef5a5b02011-11-29 18:05:07 +0000243#define CONFIG_SYS_NUM_IRQS 16
244
245/*-----------------------------------------------------------------------
246 * Memory organization:
247 * 32kB Stack
248 * 16kB Cache-As-RAM @ 0x19200000
249 * 256kB Monitor
250 * (128kB + Environment Sector Size) malloc pool
251 */
252#define CONFIG_SYS_STACK_SIZE (32 * 1024)
Graeme Russ8d616252012-11-27 15:38:36 +0000253#define CONFIG_SYS_CAR_ADDR 0x19200000
254#define CONFIG_SYS_CAR_SIZE (16 * 1024)
Gabe Blackef5a5b02011-11-29 18:05:07 +0000255#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
256#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
257#define CONFIG_SYS_MALLOC_LEN (0x20000 + 128 * 1024)
Gabe Blackef5a5b02011-11-29 18:05:07 +0000258
259
260/* allow to overwrite serial and ethaddr */
261#define CONFIG_ENV_OVERWRITE
262
263/*-----------------------------------------------------------------------
264 * FLASH configuration
265 */
Simon Glasse30bd5c2013-03-11 06:08:11 +0000266#define CONFIG_ICH_SPI
267#define CONFIG_SPI_FLASH
268#define CONFIG_SPI_FLASH_MACRONIX
269#define CONFIG_SPI_FLASH_WINBOND
270#define CONFIG_SPI_FLASH_GIGADEVICE
Gabe Blackef5a5b02011-11-29 18:05:07 +0000271#define CONFIG_SYS_NO_FLASH
Simon Glasse30bd5c2013-03-11 06:08:11 +0000272#define CONFIG_CMD_SF
273#define CONFIG_CMD_SF_TEST
274#define CONFIG_CMD_SPI
275#define CONFIG_SPI
Gabe Blackef5a5b02011-11-29 18:05:07 +0000276
277/*-----------------------------------------------------------------------
278 * Environment configuration
279 */
280#define CONFIG_ENV_IS_NOWHERE
281#define CONFIG_ENV_SIZE 0x01000
282
283/*-----------------------------------------------------------------------
284 * PCI configuration
285 */
286#define CONFIG_PCI
287
Simon Glass0641ce52013-03-06 14:08:35 +0000288/*-----------------------------------------------------------------------
289 * USB configuration
290 */
291#define CONFIG_USB_EHCI
292#define CONFIG_USB_EHCI_PCI
293#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 12
294#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
295#define CONFIG_USB_STORAGE
296#define CONFIG_USB_KEYBOARD
297#define CONFIG_SYS_USB_EVENT_POLL
298
299#define CONFIG_USB_HOST_ETHER
300#define CONFIG_USB_ETHER_ASIX
301#define CONFIG_USB_ETHER_SMSC95XX
302
303#define CONFIG_CMD_USB
304
Simon Glass420a2ca2012-11-29 09:58:58 +0000305#define CONFIG_EXTRA_ENV_SETTINGS \
306 CONFIG_STD_DEVICES_SETTINGS
307
Gabe Blackef5a5b02011-11-29 18:05:07 +0000308#endif /* __CONFIG_H */