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Prafulla Wadaskar91315892009-06-14 22:33:46 +05301/*
2 * (C) Copyright 2009
3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 *
6 * (C) Copyright 2003
7 * Ingo Assmus <ingo.assmus@keymile.com>
8 *
9 * based on - Driver for MV64360X ethernet ports
10 * Copyright (C) 2002 rabeeh@galileo.co.il
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
28 * MA 02110-1301 USA
29 */
30
31#include <common.h>
32#include <net.h>
33#include <malloc.h>
34#include <miiphy.h>
Lei Wena7efd712011-10-18 20:11:42 +053035#include <asm/io.h>
Prafulla Wadaskar91315892009-06-14 22:33:46 +053036#include <asm/errno.h>
37#include <asm/types.h>
Lei Wena7efd712011-10-18 20:11:42 +053038#include <asm/system.h>
Prafulla Wadaskar91315892009-06-14 22:33:46 +053039#include <asm/byteorder.h>
Anatolij Gustschin36aaa912011-10-29 10:09:22 +000040#include <asm/arch/cpu.h>
Albert Aribaudd44265a2010-07-12 22:24:28 +020041
42#if defined(CONFIG_KIRKWOOD)
Prafulla Wadaskar91315892009-06-14 22:33:46 +053043#include <asm/arch/kirkwood.h>
Albert Aribaudd3c9ffd2010-07-12 22:24:29 +020044#elif defined(CONFIG_ORION5X)
45#include <asm/arch/orion5x.h>
Albert Aribaudd44265a2010-07-12 22:24:28 +020046#endif
47
Albert Aribaud9b6bcdc2010-07-12 22:24:27 +020048#include "mvgbe.h"
Prafulla Wadaskar91315892009-06-14 22:33:46 +053049
Albert Aribaud49fa6ed2010-07-05 20:15:25 +020050DECLARE_GLOBAL_DATA_PTR;
51
Albert Aribaudd44265a2010-07-12 22:24:28 +020052#define MV_PHY_ADR_REQUEST 0xee
53#define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
Simon Kagstrombb1ca3b2009-08-20 10:12:28 +020054
Stefan Biglercc796972012-03-26 00:02:13 +000055#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
Prafulla Wadaskar91315892009-06-14 22:33:46 +053056/*
57 * smi_reg_read - miiphy_read callback function.
58 *
59 * Returns 16bit phy register value, or 0xffff on error
60 */
Mike Frysinger5700bb62010-07-27 18:35:08 -040061static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
Prafulla Wadaskar91315892009-06-14 22:33:46 +053062{
63 struct eth_device *dev = eth_get_dev_by_name(devname);
Albert Aribaudd44265a2010-07-12 22:24:28 +020064 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
65 struct mvgbe_registers *regs = dmvgbe->regs;
Prafulla Wadaskar91315892009-06-14 22:33:46 +053066 u32 smi_reg;
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +020067 u32 timeout;
Prafulla Wadaskar91315892009-06-14 22:33:46 +053068
69 /* Phyadr read request */
Albert Aribaudd44265a2010-07-12 22:24:28 +020070 if (phy_adr == MV_PHY_ADR_REQUEST &&
71 reg_ofs == MV_PHY_ADR_REQUEST) {
Prafulla Wadaskar91315892009-06-14 22:33:46 +053072 /* */
Albert Aribaudd44265a2010-07-12 22:24:28 +020073 *data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK);
Prafulla Wadaskar91315892009-06-14 22:33:46 +053074 return 0;
75 }
76 /* check parameters */
77 if (phy_adr > PHYADR_MASK) {
78 printf("Err..(%s) Invalid PHY address %d\n",
79 __FUNCTION__, phy_adr);
80 return -EFAULT;
81 }
82 if (reg_ofs > PHYREG_MASK) {
83 printf("Err..(%s) Invalid register offset %d\n",
84 __FUNCTION__, reg_ofs);
85 return -EFAULT;
86 }
87
Albert Aribaudd44265a2010-07-12 22:24:28 +020088 timeout = MVGBE_PHY_SMI_TIMEOUT;
Prafulla Wadaskar91315892009-06-14 22:33:46 +053089 /* wait till the SMI is not busy */
90 do {
91 /* read smi register */
Albert Aribaudd44265a2010-07-12 22:24:28 +020092 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
Prafulla Wadaskar91315892009-06-14 22:33:46 +053093 if (timeout-- == 0) {
94 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
95 return -EFAULT;
96 }
Albert Aribaudd44265a2010-07-12 22:24:28 +020097 } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
Prafulla Wadaskar91315892009-06-14 22:33:46 +053098
99 /* fill the phy address and regiser offset and read opcode */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200100 smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
101 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS)
102 | MVGBE_PHY_SMI_OPCODE_READ;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530103
104 /* write the smi register */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200105 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530106
107 /*wait till read value is ready */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200108 timeout = MVGBE_PHY_SMI_TIMEOUT;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530109
110 do {
111 /* read smi register */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200112 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530113 if (timeout-- == 0) {
114 printf("Err..(%s) SMI read ready timeout\n",
115 __FUNCTION__);
116 return -EFAULT;
117 }
Albert Aribaudd44265a2010-07-12 22:24:28 +0200118 } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530119
120 /* Wait for the data to update in the SMI register */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200121 for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++)
122 ;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530123
Albert Aribaudd44265a2010-07-12 22:24:28 +0200124 *data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530125
126 debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
127 reg_ofs, *data);
128
129 return 0;
130}
131
132/*
133 * smi_reg_write - imiiphy_write callback function.
134 *
135 * Returns 0 if write succeed, -EINVAL on bad parameters
136 * -ETIME on timeout
137 */
Mike Frysinger5700bb62010-07-27 18:35:08 -0400138static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530139{
140 struct eth_device *dev = eth_get_dev_by_name(devname);
Albert Aribaudd44265a2010-07-12 22:24:28 +0200141 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
142 struct mvgbe_registers *regs = dmvgbe->regs;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530143 u32 smi_reg;
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200144 u32 timeout;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530145
146 /* Phyadr write request*/
Albert Aribaudd44265a2010-07-12 22:24:28 +0200147 if (phy_adr == MV_PHY_ADR_REQUEST &&
148 reg_ofs == MV_PHY_ADR_REQUEST) {
149 MVGBE_REG_WR(regs->phyadr, data);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530150 return 0;
151 }
152
153 /* check parameters */
154 if (phy_adr > PHYADR_MASK) {
155 printf("Err..(%s) Invalid phy address\n", __FUNCTION__);
156 return -EINVAL;
157 }
158 if (reg_ofs > PHYREG_MASK) {
159 printf("Err..(%s) Invalid register offset\n", __FUNCTION__);
160 return -EINVAL;
161 }
162
163 /* wait till the SMI is not busy */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200164 timeout = MVGBE_PHY_SMI_TIMEOUT;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530165 do {
166 /* read smi register */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200167 smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530168 if (timeout-- == 0) {
169 printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
170 return -ETIME;
171 }
Albert Aribaudd44265a2010-07-12 22:24:28 +0200172 } while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530173
174 /* fill the phy addr and reg offset and write opcode and data */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200175 smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);
176 smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
177 | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS);
178 smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530179
180 /* write the smi register */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200181 MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530182
183 return 0;
184}
Stefan Biglercc796972012-03-26 00:02:13 +0000185#endif
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530186
187/* Stop and checks all queues */
188static void stop_queue(u32 * qreg)
189{
190 u32 reg_data;
191
192 reg_data = readl(qreg);
193
194 if (reg_data & 0xFF) {
195 /* Issue stop command for active channels only */
196 writel((reg_data << 8), qreg);
197
198 /* Wait for all queue activity to terminate. */
199 do {
200 /*
201 * Check port cause register that all queues
202 * are stopped
203 */
204 reg_data = readl(qreg);
205 }
206 while (reg_data & 0xFF);
207 }
208}
209
210/*
211 * set_access_control - Config address decode parameters for Ethernet unit
212 *
213 * This function configures the address decode parameters for the Gigabit
214 * Ethernet Controller according the given parameters struct.
215 *
216 * @regs Register struct pointer.
217 * @param Address decode parameter struct.
218 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200219static void set_access_control(struct mvgbe_registers *regs,
220 struct mvgbe_winparam *param)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530221{
222 u32 access_prot_reg;
223
224 /* Set access control register */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200225 access_prot_reg = MVGBE_REG_RD(regs->epap);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530226 /* clear window permission */
227 access_prot_reg &= (~(3 << (param->win * 2)));
228 access_prot_reg |= (param->access_ctrl << (param->win * 2));
Albert Aribaudd44265a2010-07-12 22:24:28 +0200229 MVGBE_REG_WR(regs->epap, access_prot_reg);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530230
231 /* Set window Size reg (SR) */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200232 MVGBE_REG_WR(regs->barsz[param->win].size,
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530233 (((param->size / 0x10000) - 1) << 16));
234
235 /* Set window Base address reg (BA) */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200236 MVGBE_REG_WR(regs->barsz[param->win].bar,
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530237 (param->target | param->attrib | param->base_addr));
238 /* High address remap reg (HARR) */
239 if (param->win < 4)
Albert Aribaudd44265a2010-07-12 22:24:28 +0200240 MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530241
242 /* Base address enable reg (BARER) */
243 if (param->enable == 1)
Albert Aribaudd44265a2010-07-12 22:24:28 +0200244 MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530245 else
Albert Aribaudd44265a2010-07-12 22:24:28 +0200246 MVGBE_REG_BITS_SET(regs->bare, (1 << param->win));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530247}
248
Albert Aribaudd44265a2010-07-12 22:24:28 +0200249static void set_dram_access(struct mvgbe_registers *regs)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530250{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200251 struct mvgbe_winparam win_param;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530252 int i;
253
254 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
255 /* Set access parameters for DRAM bank i */
256 win_param.win = i; /* Use Ethernet window i */
257 /* Window target - DDR */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200258 win_param.target = MVGBE_TARGET_DRAM;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530259 /* Enable full access */
260 win_param.access_ctrl = EWIN_ACCESS_FULL;
261 win_param.high_addr = 0;
Albert Aribaud49fa6ed2010-07-05 20:15:25 +0200262 /* Get bank base and size */
263 win_param.base_addr = gd->bd->bi_dram[i].start;
264 win_param.size = gd->bd->bi_dram[i].size;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530265 if (win_param.size == 0)
266 win_param.enable = 0;
267 else
268 win_param.enable = 1; /* Enable the access */
269
270 /* Enable DRAM bank */
271 switch (i) {
272 case 0:
273 win_param.attrib = EBAR_DRAM_CS0;
274 break;
275 case 1:
276 win_param.attrib = EBAR_DRAM_CS1;
277 break;
278 case 2:
279 win_param.attrib = EBAR_DRAM_CS2;
280 break;
281 case 3:
282 win_param.attrib = EBAR_DRAM_CS3;
283 break;
284 default:
Albert Aribaud49fa6ed2010-07-05 20:15:25 +0200285 /* invalid bank, disable access */
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530286 win_param.enable = 0;
287 win_param.attrib = 0;
288 break;
289 }
290 /* Set the access control for address window(EPAPR) RD/WR */
291 set_access_control(regs, &win_param);
292 }
293}
294
295/*
296 * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
297 *
298 * Go through all the DA filter tables (Unicast, Special Multicast & Other
299 * Multicast) and set each entry to 0.
300 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200301static void port_init_mac_tables(struct mvgbe_registers *regs)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530302{
303 int table_index;
304
305 /* Clear DA filter unicast table (Ex_dFUT) */
306 for (table_index = 0; table_index < 4; ++table_index)
Albert Aribaudd44265a2010-07-12 22:24:28 +0200307 MVGBE_REG_WR(regs->dfut[table_index], 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530308
309 for (table_index = 0; table_index < 64; ++table_index) {
310 /* Clear DA filter special multicast table (Ex_dFSMT) */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200311 MVGBE_REG_WR(regs->dfsmt[table_index], 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530312 /* Clear DA filter other multicast table (Ex_dFOMT) */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200313 MVGBE_REG_WR(regs->dfomt[table_index], 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530314 }
315}
316
317/*
318 * port_uc_addr - This function Set the port unicast address table
319 *
320 * This function locates the proper entry in the Unicast table for the
321 * specified MAC nibble and sets its properties according to function
322 * parameters.
323 * This function add/removes MAC addresses from the port unicast address
324 * table.
325 *
326 * @uc_nibble Unicast MAC Address last nibble.
327 * @option 0 = Add, 1 = remove address.
328 *
329 * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
330 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200331static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble,
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530332 int option)
333{
334 u32 unicast_reg;
335 u32 tbl_offset;
336 u32 reg_offset;
337
338 /* Locate the Unicast table entry */
339 uc_nibble = (0xf & uc_nibble);
340 /* Register offset from unicast table base */
341 tbl_offset = (uc_nibble / 4);
342 /* Entry offset within the above register */
343 reg_offset = uc_nibble % 4;
344
345 switch (option) {
346 case REJECT_MAC_ADDR:
347 /*
348 * Clear accepts frame bit at specified unicast
349 * DA table entry
350 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200351 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530352 unicast_reg &= (0xFF << (8 * reg_offset));
Albert Aribaudd44265a2010-07-12 22:24:28 +0200353 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530354 break;
355 case ACCEPT_MAC_ADDR:
356 /* Set accepts frame bit at unicast DA filter table entry */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200357 unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530358 unicast_reg &= (0xFF << (8 * reg_offset));
359 unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
Albert Aribaudd44265a2010-07-12 22:24:28 +0200360 MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530361 break;
362 default:
363 return 0;
364 }
365 return 1;
366}
367
368/*
369 * port_uc_addr_set - This function Set the port Unicast address.
370 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200371static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530372{
373 u32 mac_h;
374 u32 mac_l;
375
376 mac_l = (p_addr[4] << 8) | (p_addr[5]);
377 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
378 (p_addr[3] << 0);
379
Albert Aribaudd44265a2010-07-12 22:24:28 +0200380 MVGBE_REG_WR(regs->macal, mac_l);
381 MVGBE_REG_WR(regs->macah, mac_h);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530382
383 /* Accept frames of this address */
384 port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
385}
386
387/*
Albert Aribaudd44265a2010-07-12 22:24:28 +0200388 * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530389 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200390static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530391{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200392 struct mvgbe_rxdesc *p_rx_desc;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530393 int i;
394
395 /* initialize the Rx descriptors ring */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200396 p_rx_desc = dmvgbe->p_rxdesc;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530397 for (i = 0; i < RINGSZ; i++) {
398 p_rx_desc->cmd_sts =
Albert Aribaudd44265a2010-07-12 22:24:28 +0200399 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530400 p_rx_desc->buf_size = PKTSIZE_ALIGN;
401 p_rx_desc->byte_cnt = 0;
Albert Aribaudd44265a2010-07-12 22:24:28 +0200402 p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530403 if (i == (RINGSZ - 1))
Albert Aribaudd44265a2010-07-12 22:24:28 +0200404 p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530405 else {
Albert Aribaudd44265a2010-07-12 22:24:28 +0200406 p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *)
407 ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530408 p_rx_desc = p_rx_desc->nxtdesc_p;
409 }
410 }
Albert Aribaudd44265a2010-07-12 22:24:28 +0200411 dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530412}
413
Albert Aribaudd44265a2010-07-12 22:24:28 +0200414static int mvgbe_init(struct eth_device *dev)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530415{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200416 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
417 struct mvgbe_registers *regs = dmvgbe->regs;
Prafulla Wadaskaraba82372009-09-09 15:59:19 +0530418#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
419 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
Simon Kagstromcad713b2009-08-20 10:13:06 +0200420 int i;
Prafulla Wadaskaraba82372009-09-09 15:59:19 +0530421#endif
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530422 /* setup RX rings */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200423 mvgbe_init_rx_desc_ring(dmvgbe);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530424
425 /* Clear the ethernet port interrupts */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200426 MVGBE_REG_WR(regs->ic, 0);
427 MVGBE_REG_WR(regs->ice, 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530428 /* Unmask RX buffer and TX end interrupt */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200429 MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530430 /* Unmask phy and link status changes interrupts */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200431 MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530432
433 set_dram_access(regs);
434 port_init_mac_tables(regs);
Albert Aribaudd44265a2010-07-12 22:24:28 +0200435 port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530436
437 /* Assign port configuration and command. */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200438 MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
439 MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
440 MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530441
442 /* Assign port SDMA configuration */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200443 MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
444 MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
445 MVGBE_REG_WR(regs->tqx[0].tqxtbc,
446 (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530447 /* Turn off the port/RXUQ bandwidth limitation */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200448 MVGBE_REG_WR(regs->pmtu, 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530449
450 /* Set maximum receive buffer to 9700 bytes */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200451 MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
452 | (MVGBE_REG_RD(regs->psc0) & MRU_MASK));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530453
Prafulla Wadaskarf0588fd2010-04-06 21:33:08 +0530454 /* Enable port initially */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200455 MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);
Prafulla Wadaskarf0588fd2010-04-06 21:33:08 +0530456
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530457 /*
458 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
459 * disable the leaky bucket mechanism .
460 */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200461 MVGBE_REG_WR(regs->pmtu, 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530462
463 /* Assignment of Rx CRDB of given RXUQ */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200464 MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
Albert Aribaudc19a20d2010-07-10 15:41:29 +0200465 /* ensure previous write is done before enabling Rx DMA */
466 isb();
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530467 /* Enable port Rx. */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200468 MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530469
470#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
471 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
Simon Kagstromcad713b2009-08-20 10:13:06 +0200472 /* Wait up to 5s for the link status */
473 for (i = 0; i < 5; i++) {
474 u16 phyadr;
475
Albert Aribaudd44265a2010-07-12 22:24:28 +0200476 miiphy_read(dev->name, MV_PHY_ADR_REQUEST,
477 MV_PHY_ADR_REQUEST, &phyadr);
Simon Kagstromcad713b2009-08-20 10:13:06 +0200478 /* Return if we get link up */
479 if (miiphy_link(dev->name, phyadr))
480 return 0;
481 udelay(1000000);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530482 }
Simon Kagstromcad713b2009-08-20 10:13:06 +0200483
484 printf("No link on %s\n", dev->name);
485 return -1;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530486#endif
487 return 0;
488}
489
Albert Aribaudd44265a2010-07-12 22:24:28 +0200490static int mvgbe_halt(struct eth_device *dev)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530491{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200492 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
493 struct mvgbe_registers *regs = dmvgbe->regs;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530494
495 /* Disable all gigE address decoder */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200496 MVGBE_REG_WR(regs->bare, 0x3f);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530497
498 stop_queue(&regs->tqc);
499 stop_queue(&regs->rqc);
500
Prafulla Wadaskarf0588fd2010-04-06 21:33:08 +0530501 /* Disable port */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200502 MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530503 /* Set port is not reset */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200504 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530505#ifdef CONFIG_SYS_MII_MODE
506 /* Set MMI interface up */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200507 MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530508#endif
509 /* Disable & mask ethernet port interrupts */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200510 MVGBE_REG_WR(regs->ic, 0);
511 MVGBE_REG_WR(regs->ice, 0);
512 MVGBE_REG_WR(regs->pim, 0);
513 MVGBE_REG_WR(regs->peim, 0);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530514
515 return 0;
516}
517
Albert Aribaudd44265a2010-07-12 22:24:28 +0200518static int mvgbe_write_hwaddr(struct eth_device *dev)
Prafulla Wadaskarb5ce63e2010-04-06 22:21:33 +0530519{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200520 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
521 struct mvgbe_registers *regs = dmvgbe->regs;
Prafulla Wadaskarb5ce63e2010-04-06 22:21:33 +0530522
523 /* Programs net device MAC address after initialization */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200524 port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
Prafulla Wadaskarb5ce63e2010-04-06 22:21:33 +0530525 return 0;
526}
527
Albert Aribaudd44265a2010-07-12 22:24:28 +0200528static int mvgbe_send(struct eth_device *dev, void *dataptr,
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530529 int datasize)
530{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200531 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
532 struct mvgbe_registers *regs = dmvgbe->regs;
533 struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
Simon Kagstrom477fa632009-08-20 10:14:11 +0200534 void *p = (void *)dataptr;
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200535 u32 cmd_sts;
Anatolij Gustschine6e556c2011-11-19 08:59:36 +0000536 u32 txuq0_reg_addr;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530537
Simon Kagstrom477fa632009-08-20 10:14:11 +0200538 /* Copy buffer if it's misaligned */
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530539 if ((u32) dataptr & 0x07) {
Simon Kagstrom477fa632009-08-20 10:14:11 +0200540 if (datasize > PKTSIZE_ALIGN) {
541 printf("Non-aligned data too large (%d)\n",
542 datasize);
543 return -1;
544 }
545
Albert Aribaudd44265a2010-07-12 22:24:28 +0200546 memcpy(dmvgbe->p_aligned_txbuf, p, datasize);
547 p = dmvgbe->p_aligned_txbuf;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530548 }
Simon Kagstrom477fa632009-08-20 10:14:11 +0200549
Albert Aribaudd44265a2010-07-12 22:24:28 +0200550 p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC;
551 p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC;
552 p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA;
553 p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT;
Simon Kagstrom477fa632009-08-20 10:14:11 +0200554 p_txdesc->buf_ptr = (u8 *) p;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530555 p_txdesc->byte_cnt = datasize;
556
Albert Aribaudc19a20d2010-07-10 15:41:29 +0200557 /* Set this tc desc as zeroth TXUQ */
Anatolij Gustschine6e556c2011-11-19 08:59:36 +0000558 txuq0_reg_addr = (u32)&regs->tcqdp[TXUQ];
559 writel((u32) p_txdesc, txuq0_reg_addr);
Albert Aribaudc19a20d2010-07-10 15:41:29 +0200560
561 /* ensure tx desc writes above are performed before we start Tx DMA */
562 isb();
563
564 /* Apply send command using zeroth TXUQ */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200565 MVGBE_REG_WR(regs->tqc, (1 << TXUQ));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530566
567 /*
568 * wait for packet xmit completion
569 */
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200570 cmd_sts = readl(&p_txdesc->cmd_sts);
Albert Aribaudd44265a2010-07-12 22:24:28 +0200571 while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530572 /* return fail if error is detected */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200573 if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) ==
574 (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) &&
575 cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530576 printf("Err..(%s) in xmit packet\n", __FUNCTION__);
577 return -1;
578 }
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200579 cmd_sts = readl(&p_txdesc->cmd_sts);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530580 };
581 return 0;
582}
583
Albert Aribaudd44265a2010-07-12 22:24:28 +0200584static int mvgbe_recv(struct eth_device *dev)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530585{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200586 struct mvgbe_device *dmvgbe = to_mvgbe(dev);
587 struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200588 u32 cmd_sts;
589 u32 timeout = 0;
Anatolij Gustschine6e556c2011-11-19 08:59:36 +0000590 u32 rxdesc_curr_addr;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530591
592 /* wait untill rx packet available or timeout */
593 do {
Albert Aribaudd44265a2010-07-12 22:24:28 +0200594 if (timeout < MVGBE_PHY_SMI_TIMEOUT)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530595 timeout++;
596 else {
597 debug("%s time out...\n", __FUNCTION__);
598 return -1;
599 }
Albert Aribaudd44265a2010-07-12 22:24:28 +0200600 } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530601
602 if (p_rxdesc_curr->byte_cnt != 0) {
603 debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
604 __FUNCTION__, (u32) p_rxdesc_curr->byte_cnt,
605 (u32) p_rxdesc_curr->buf_ptr,
606 (u32) p_rxdesc_curr->cmd_sts);
607 }
608
609 /*
610 * In case received a packet without first/last bits on
611 * OR the error summary bit is on,
612 * the packets needs to be dropeed.
613 */
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200614 cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
615
616 if ((cmd_sts &
Albert Aribaudd44265a2010-07-12 22:24:28 +0200617 (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC))
618 != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530619
620 printf("Err..(%s) Dropping packet spread on"
621 " multiple descriptors\n", __FUNCTION__);
622
Albert Aribaudd44265a2010-07-12 22:24:28 +0200623 } else if (cmd_sts & MVGBE_ERROR_SUMMARY) {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530624
625 printf("Err..(%s) Dropping packet with errors\n",
626 __FUNCTION__);
627
628 } else {
629 /* !!! call higher layer processing */
630 debug("%s: Sending Received packet to"
631 " upper layer (NetReceive)\n", __FUNCTION__);
632
633 /* let the upper layer handle the packet */
634 NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
635 (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
636 }
637 /*
638 * free these descriptors and point next in the ring
639 */
640 p_rxdesc_curr->cmd_sts =
Albert Aribaudd44265a2010-07-12 22:24:28 +0200641 MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530642 p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
643 p_rxdesc_curr->byte_cnt = 0;
644
Anatolij Gustschine6e556c2011-11-19 08:59:36 +0000645 rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr;
646 writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr);
Simon Kagstrom7b05f5e2009-07-08 13:03:18 +0200647
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530648 return 0;
649}
650
Albert Aribaudd44265a2010-07-12 22:24:28 +0200651int mvgbe_initialize(bd_t *bis)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530652{
Albert Aribaudd44265a2010-07-12 22:24:28 +0200653 struct mvgbe_device *dmvgbe;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530654 struct eth_device *dev;
655 int devnum;
Albert Aribaudd44265a2010-07-12 22:24:28 +0200656 u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530657
Albert Aribaudd44265a2010-07-12 22:24:28 +0200658 for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530659 /*skip if port is configured not to use */
660 if (used_ports[devnum] == 0)
661 continue;
662
Albert Aribaudd44265a2010-07-12 22:24:28 +0200663 dmvgbe = malloc(sizeof(struct mvgbe_device));
664
665 if (!dmvgbe)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530666 goto error1;
667
Albert Aribaudd44265a2010-07-12 22:24:28 +0200668 memset(dmvgbe, 0, sizeof(struct mvgbe_device));
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530669
Albert Aribaudd44265a2010-07-12 22:24:28 +0200670 dmvgbe->p_rxdesc =
671 (struct mvgbe_rxdesc *)memalign(PKTALIGN,
672 MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1);
673
674 if (!dmvgbe->p_rxdesc)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530675 goto error2;
676
Albert Aribaudd44265a2010-07-12 22:24:28 +0200677 dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN,
678 RINGSZ*PKTSIZE_ALIGN + 1);
679
680 if (!dmvgbe->p_rxbuf)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530681 goto error3;
682
Albert Aribaudd44265a2010-07-12 22:24:28 +0200683 dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
684
685 if (!dmvgbe->p_aligned_txbuf)
Simon Kagstrom477fa632009-08-20 10:14:11 +0200686 goto error4;
687
Albert Aribaudd44265a2010-07-12 22:24:28 +0200688 dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign(
689 PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
690
691 if (!dmvgbe->p_txdesc) {
692 free(dmvgbe->p_aligned_txbuf);
693error4:
694 free(dmvgbe->p_rxbuf);
695error3:
696 free(dmvgbe->p_rxdesc);
697error2:
698 free(dmvgbe);
699error1:
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530700 printf("Err.. %s Failed to allocate memory\n",
701 __FUNCTION__);
702 return -1;
703 }
704
Albert Aribaudd44265a2010-07-12 22:24:28 +0200705 dev = &dmvgbe->dev;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530706
Mike Frysingerf6add132011-11-10 14:11:04 +0000707 /* must be less than sizeof(dev->name) */
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530708 sprintf(dev->name, "egiga%d", devnum);
709
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530710 switch (devnum) {
711 case 0:
Albert Aribaudd44265a2010-07-12 22:24:28 +0200712 dmvgbe->regs = (void *)MVGBE0_BASE;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530713 break;
Albert Aribaudd44265a2010-07-12 22:24:28 +0200714#if defined(MVGBE1_BASE)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530715 case 1:
Albert Aribaudd44265a2010-07-12 22:24:28 +0200716 dmvgbe->regs = (void *)MVGBE1_BASE;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530717 break;
Albert Aribaudd44265a2010-07-12 22:24:28 +0200718#endif
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530719 default: /* this should never happen */
720 printf("Err..(%s) Invalid device number %d\n",
721 __FUNCTION__, devnum);
722 return -1;
723 }
724
Albert Aribaudd44265a2010-07-12 22:24:28 +0200725 dev->init = (void *)mvgbe_init;
726 dev->halt = (void *)mvgbe_halt;
727 dev->send = (void *)mvgbe_send;
728 dev->recv = (void *)mvgbe_recv;
729 dev->write_hwaddr = (void *)mvgbe_write_hwaddr;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530730
731 eth_register(dev);
732
733#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
734 miiphy_register(dev->name, smi_reg_read, smi_reg_write);
735 /* Set phy address of the port */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200736 miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
737 MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530738#endif
739 }
740 return 0;
Prafulla Wadaskar0b785dd2009-07-01 20:34:51 +0200741}